Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00244
Yu-hsin Liu, Yi Jing, B. Bosse, Samir Damle, Abraham Akinin, Sue Bauchner, H. Thacker
We report on the assembly process and reliability test development of a flexible, biocompatible optoelectronic neural stimulator for a retinal prosthesis. The design and development process for the flexible circuit are discussed. The successful bonding process between six silicon dielets and flexible substrates is presented. The characterization and accelerated lifetime testing are also detailed. The integration techniques described herein may be used to scale up the existing electrode array or for next generation higher visual acuity retinal prostheses. In addition, the methods and setup for lifetime testing may be used in the development of other optoelectronic flexible neural interfaces.
{"title":"Assembly Development of a Highly Flexible and Biocompatible Optoelectronic Neural Stimulator for Implantable Retinal Prosthesis","authors":"Yu-hsin Liu, Yi Jing, B. Bosse, Samir Damle, Abraham Akinin, Sue Bauchner, H. Thacker","doi":"10.1109/ECTC32696.2021.00244","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00244","url":null,"abstract":"We report on the assembly process and reliability test development of a flexible, biocompatible optoelectronic neural stimulator for a retinal prosthesis. The design and development process for the flexible circuit are discussed. The successful bonding process between six silicon dielets and flexible substrates is presented. The characterization and accelerated lifetime testing are also detailed. The integration techniques described herein may be used to scale up the existing electrode array or for next generation higher visual acuity retinal prostheses. In addition, the methods and setup for lifetime testing may be used in the development of other optoelectronic flexible neural interfaces.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00261
Ying‐Chen Chen, J. Eshraghian, Isaiah Shipley, Maxwell Weiss
New computational paradigms are required to overcome the von-Neumann bottleneck by reducing main memory access. Neuromorphic and in-memory computing has brought on much promise for improving efficiency in a subset of tasks, and emerging memory technologies are inextricably tied to localized memory accesses. However, the sneak path current (SPC) through unselected neighboring cells is a major challenge occurring in high density storage application in the crossbar array configuration. In this work, carbon-based self-selective memory is shown to overcome the SPC problem and additionally is demonstrated to be a potential candidate as a nanodevice for resource-constrained in-memory supervised learning, by taking advantage of its analog synaptic behaviors. Device variation and non-idealities are characterized in the context of neural network regularization, in fulfilling the aim to reduce the ever-increasing power demands of modern computing.
{"title":"Analog Synaptic Behaviors in Carbon-Based Self-Selective RRAM for In-Memory Supervised Learning","authors":"Ying‐Chen Chen, J. Eshraghian, Isaiah Shipley, Maxwell Weiss","doi":"10.1109/ECTC32696.2021.00261","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00261","url":null,"abstract":"New computational paradigms are required to overcome the von-Neumann bottleneck by reducing main memory access. Neuromorphic and in-memory computing has brought on much promise for improving efficiency in a subset of tasks, and emerging memory technologies are inextricably tied to localized memory accesses. However, the sneak path current (SPC) through unselected neighboring cells is a major challenge occurring in high density storage application in the crossbar array configuration. In this work, carbon-based self-selective memory is shown to overcome the SPC problem and additionally is demonstrated to be a potential candidate as a nanodevice for resource-constrained in-memory supervised learning, by taking advantage of its analog synaptic behaviors. Device variation and non-idealities are characterized in the context of neural network regularization, in fulfilling the aim to reduce the ever-increasing power demands of modern computing.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115650431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00134
Ryosuke Yamazaki, K. Ozaki, Toru Imaizumi, Hidenori Matsuhima, Masayuki Hayashi, S. Yamamoto, Yoshito Ushio
Silicone materials are well recognized for their excellent photo/thermal stability, owing to which they are often used as adhesives or encapsulants in electronics applications. However, silicone materials can also present a challenge due to their high Coefficient of Thermal Expansion (CTE) which can generate thermal stress because of CTE mismatching with the substrate. While a “soft” silicone compensates for CTE mismatch through deformation during thermal stress in a device setting, this mismatch limits the use of “hard” silicone products in the market (this limitation was the first market need we addressed in our study). On the other hand, readily available silicone adhesives or encapsulants are mostly curable liquid or paste forms. Organic counterparts such as epoxy or acrylic materials offer “hotmelt” products to cover specific market needs in transfer molding (cylindrical tablet) or large area encapsulation (film/sheet). While the market demand for curable silicone hotmelt products is emerging, only a few such products have been realized thus far (this unmet demand is the second market need we investigated). Our recent study on silicone hotmelt has shown that thermal stress management is feasible even with silicone compositions producing relatively “hard” cured monolith; silicone hotmelt enables an extreme ratio of the raw materials, which is impossible by typical curable liquid compositions. In this presentation, we will introduce novel silicone hotmelt solutions to meet emerging urgent technological requirements such as ease of handling, thermal stability or reliability against thermal stress. The first solution is heat curable silicone hotmelt cylindrical tablet for transfer molding. This aims to achieve similar handling/property to epoxy molding compound (EMC) tablet with superior thermal stability. Silicone hotmelt technology combined with novel compounding technology enabled extreme hardness and CTE of the cured piece; it provides a tensile modulus of 8 GPa and a CTE of as low as 11 ppm/°C, which are comparable to typical EMC. It has been confirmed that molded piece with a PCB board did not show any warpage, indicating matched CTEs in a molded body. Furthermore, the prototype showed no significant degeneration in mechanical and adhesive properties up to 1000-hour exposure to 250°C. In conjunction with optimized melt/flow performance of the prototype, this can be a novel solution for electronics encapsulant applications requiring extreme thermal stability. The second solution is heat curable silicone hotmelt film for large area encapsulation or adhesion. Large area molding is an emerging trend in electronics to achieve higher production output. Utilizing curable liquid products in this application is cumbersome because it requires dam material for precise control of the layer thickness. Furthermore, CTE mismatch between silicone and the substrate becomes a serious issue because of the relatively large thermal stress coming from the large
{"title":"Novel Silicone Hotmelt Solutions for Electronic Components","authors":"Ryosuke Yamazaki, K. Ozaki, Toru Imaizumi, Hidenori Matsuhima, Masayuki Hayashi, S. Yamamoto, Yoshito Ushio","doi":"10.1109/ECTC32696.2021.00134","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00134","url":null,"abstract":"Silicone materials are well recognized for their excellent photo/thermal stability, owing to which they are often used as adhesives or encapsulants in electronics applications. However, silicone materials can also present a challenge due to their high Coefficient of Thermal Expansion (CTE) which can generate thermal stress because of CTE mismatching with the substrate. While a “soft” silicone compensates for CTE mismatch through deformation during thermal stress in a device setting, this mismatch limits the use of “hard” silicone products in the market (this limitation was the first market need we addressed in our study). On the other hand, readily available silicone adhesives or encapsulants are mostly curable liquid or paste forms. Organic counterparts such as epoxy or acrylic materials offer “hotmelt” products to cover specific market needs in transfer molding (cylindrical tablet) or large area encapsulation (film/sheet). While the market demand for curable silicone hotmelt products is emerging, only a few such products have been realized thus far (this unmet demand is the second market need we investigated). Our recent study on silicone hotmelt has shown that thermal stress management is feasible even with silicone compositions producing relatively “hard” cured monolith; silicone hotmelt enables an extreme ratio of the raw materials, which is impossible by typical curable liquid compositions. In this presentation, we will introduce novel silicone hotmelt solutions to meet emerging urgent technological requirements such as ease of handling, thermal stability or reliability against thermal stress. The first solution is heat curable silicone hotmelt cylindrical tablet for transfer molding. This aims to achieve similar handling/property to epoxy molding compound (EMC) tablet with superior thermal stability. Silicone hotmelt technology combined with novel compounding technology enabled extreme hardness and CTE of the cured piece; it provides a tensile modulus of 8 GPa and a CTE of as low as 11 ppm/°C, which are comparable to typical EMC. It has been confirmed that molded piece with a PCB board did not show any warpage, indicating matched CTEs in a molded body. Furthermore, the prototype showed no significant degeneration in mechanical and adhesive properties up to 1000-hour exposure to 250°C. In conjunction with optimized melt/flow performance of the prototype, this can be a novel solution for electronics encapsulant applications requiring extreme thermal stability. The second solution is heat curable silicone hotmelt film for large area encapsulation or adhesion. Large area molding is an emerging trend in electronics to achieve higher production output. Utilizing curable liquid products in this application is cumbersome because it requires dam material for precise control of the layer thickness. Furthermore, CTE mismatch between silicone and the substrate becomes a serious issue because of the relatively large thermal stress coming from the large","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117125234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00023
John F. Chang, Jian Lu, Burhan Ali
5G, HPC, AI and IoT applications are current market drivers. These drive the demand for heterogeneous integration because they require high performance, integrated functionality and limited device size for next generation production. Fan-out panel level packaging (FOPLP) is one of the technologies that has the potential to meet all of these packaging requirements. According to Yole Développement's analysis, the FOPLP market size will increase to $2.79 hundred million with 79% CAGR, showing that more manufacturers are adopting FOPLP. Although FOPLP is one of the advanced packaging technologies that has potential to achieve the market drivers' requirements, it also faces significant process challenges. One of the critical challenges is reconstituted die placement error that induces low yield. FOPLP requires KGDs (known good die) transfer from the resource wafers to a panel carriage, these reconstituted dies suffer displacement errors from the nominal position because of pick and place error and the epoxy molding compound processes. In order to achieve acceptable yield and throughput, feedforward site by site exposure lithography was used to address these challenges in FOPLP, but a serious issue was observed with using feedforward site by site lithography; when one or above reconstituted dies' displacement error is too large, these dies affect the site/shot correction accuracy and cause low overlay accuracy to all the dies in the site/shot. To address this issue, advanced outlier control technology is utilized. This technology can precisely detect the outlier dies in the sites of a panel and take customized actions to ensure the overlay accuracy based on various process requirement. In this paper, we demonstrated “outlier die control technology using feedforward lithography” on a $510text{mm}times 515 text{mm}$ panel substrate. 400 simulation dies were built on this panel, and part of the dies were designed with a large displacement error, we ran this panel using feedforward lithography with outlier die control technology and showed how these two technologies integrated together and how this integration strategy worked for the FOPLP process. We also review and discuss the results for how this integration technology can maintain the yield and throughput under such challenging conditions.
{"title":"Advanced Outlier Die Control Technology in Fan-Out Panel Level Packaging Using Feedforward Lithography","authors":"John F. Chang, Jian Lu, Burhan Ali","doi":"10.1109/ECTC32696.2021.00023","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00023","url":null,"abstract":"5G, HPC, AI and IoT applications are current market drivers. These drive the demand for heterogeneous integration because they require high performance, integrated functionality and limited device size for next generation production. Fan-out panel level packaging (FOPLP) is one of the technologies that has the potential to meet all of these packaging requirements. According to Yole Développement's analysis, the FOPLP market size will increase to $2.79 hundred million with 79% CAGR, showing that more manufacturers are adopting FOPLP. Although FOPLP is one of the advanced packaging technologies that has potential to achieve the market drivers' requirements, it also faces significant process challenges. One of the critical challenges is reconstituted die placement error that induces low yield. FOPLP requires KGDs (known good die) transfer from the resource wafers to a panel carriage, these reconstituted dies suffer displacement errors from the nominal position because of pick and place error and the epoxy molding compound processes. In order to achieve acceptable yield and throughput, feedforward site by site exposure lithography was used to address these challenges in FOPLP, but a serious issue was observed with using feedforward site by site lithography; when one or above reconstituted dies' displacement error is too large, these dies affect the site/shot correction accuracy and cause low overlay accuracy to all the dies in the site/shot. To address this issue, advanced outlier control technology is utilized. This technology can precisely detect the outlier dies in the sites of a panel and take customized actions to ensure the overlay accuracy based on various process requirement. In this paper, we demonstrated “outlier die control technology using feedforward lithography” on a $510text{mm}times 515 text{mm}$ panel substrate. 400 simulation dies were built on this panel, and part of the dies were designed with a large displacement error, we ran this panel using feedforward lithography with outlier die control technology and showed how these two technologies integrated together and how this integration strategy worked for the FOPLP process. We also review and discuss the results for how this integration technology can maintain the yield and throughput under such challenging conditions.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120815251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00236
Davira P. Widianto, Benjamin G. Stewart, Juan Mena-Lapaix, R. Shafer, A. Burns, M. Prausnitz, A. Alizadeh, S. Sitaraman
Recently, microneedle patches have been explored for extracting interstitial fluid with the goal of extracting temporally relevant, clinical-grade information for human health monitoring. As compared to traditional hypodermic needles, the sub-millimeter scale of microneedles allows for the creation of micropores providing access into human skin interstitial fluid while minimizing interactions with blood vessels and nerves, leading to painless insertion with little to no bleeding. An essential sub-component is the actuator, responsible for driving the microneedle into the skin with a precise force and velocity to ensure reliable insertion. Reliability, in this case, consists of two criteria: the ability of the microneedle to 1) penetrate the skin, and 2) withstand penetration forces without mechanical failure. Evaluation of these criteria requires a thorough understanding of the non-linear, time-dependent interactions between the microneedle and the skin during insertion, including rupture and tearing of the skin on the micron scale, and the resultant stresses on the microneedle. To this end, a comprehensive finite-element model was developed to simulate the microneedle insertion process. This analysis yielded a prediction of complete microneedle insertion without failure of the microneedle and an estimated insertion force of 0.055 N per microneedle, well within the capability of the actuator system considered. This insertion force was validated using experimental data obtained through microneedle insertion in whole skin samples. The model was then used to perform several parametric studies, yielding valuable insights for possible future design improvements.
{"title":"Microneedle Insertion into Visco-Hyperelastic Model for Skin for Healthcare Application","authors":"Davira P. Widianto, Benjamin G. Stewart, Juan Mena-Lapaix, R. Shafer, A. Burns, M. Prausnitz, A. Alizadeh, S. Sitaraman","doi":"10.1109/ECTC32696.2021.00236","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00236","url":null,"abstract":"Recently, microneedle patches have been explored for extracting interstitial fluid with the goal of extracting temporally relevant, clinical-grade information for human health monitoring. As compared to traditional hypodermic needles, the sub-millimeter scale of microneedles allows for the creation of micropores providing access into human skin interstitial fluid while minimizing interactions with blood vessels and nerves, leading to painless insertion with little to no bleeding. An essential sub-component is the actuator, responsible for driving the microneedle into the skin with a precise force and velocity to ensure reliable insertion. Reliability, in this case, consists of two criteria: the ability of the microneedle to 1) penetrate the skin, and 2) withstand penetration forces without mechanical failure. Evaluation of these criteria requires a thorough understanding of the non-linear, time-dependent interactions between the microneedle and the skin during insertion, including rupture and tearing of the skin on the micron scale, and the resultant stresses on the microneedle. To this end, a comprehensive finite-element model was developed to simulate the microneedle insertion process. This analysis yielded a prediction of complete microneedle insertion without failure of the microneedle and an estimated insertion force of 0.055 N per microneedle, well within the capability of the actuator system considered. This insertion force was validated using experimental data obtained through microneedle insertion in whole skin samples. The model was then used to perform several parametric studies, yielding valuable insights for possible future design improvements.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121007383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00031
G. Tang, L. Wai, Siak Boon Lim, Yong Liang Ye, B. L. Lau, Kazunori Yamamoto, Xiaowu Zhang
In this study, a novel Cu lead frame (LF) based double side cooling SiC power module is proposed and developed. The proposed SiC power module eliminates the conventional direct bonded copper (DBC) substrates by implementing a dedicated copper lead frame. Meanwhile, the proposed power module is capable for double side liquid cooling scheme by employing the flat copper clips at the top side of SiC devices. Furthermore, the high temperature endurable materials, i.e. epoxy molding compound (EMC), die attachment (DA) and lead free solder, are evaluated and identified for the proposed power module. In addition, the processes for interconnects (i.e. die attach and solder joints) formation and package encapsulation is optimized for the power module assembly. Lastly, the adhesive dielectric thermal interface material (TIM) with high thermal conductivity is recommended to bond the power module with the heat sink. The proposed power module has been fabricated with identified materials and gone through the specified reliability assessments, e.g. unbiased highly accelerated stress test (uHAST), temperature cycling (TC) test (−40∼150°C) for 1,000 cycles, high temperature storage (HTS) test at 200°C for 1,000hrs and power cycling test (PCT) ($Delta mathrm{T}=150^{circ}mathrm{C}$) for 50,000 cycles. Failure analysis has been conducted for the failed samples.
{"title":"Development of a Novel Lead Frame Based Double Side Liquid Cooling High Performance SiC Power Module","authors":"G. Tang, L. Wai, Siak Boon Lim, Yong Liang Ye, B. L. Lau, Kazunori Yamamoto, Xiaowu Zhang","doi":"10.1109/ECTC32696.2021.00031","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00031","url":null,"abstract":"In this study, a novel Cu lead frame (LF) based double side cooling SiC power module is proposed and developed. The proposed SiC power module eliminates the conventional direct bonded copper (DBC) substrates by implementing a dedicated copper lead frame. Meanwhile, the proposed power module is capable for double side liquid cooling scheme by employing the flat copper clips at the top side of SiC devices. Furthermore, the high temperature endurable materials, i.e. epoxy molding compound (EMC), die attachment (DA) and lead free solder, are evaluated and identified for the proposed power module. In addition, the processes for interconnects (i.e. die attach and solder joints) formation and package encapsulation is optimized for the power module assembly. Lastly, the adhesive dielectric thermal interface material (TIM) with high thermal conductivity is recommended to bond the power module with the heat sink. The proposed power module has been fabricated with identified materials and gone through the specified reliability assessments, e.g. unbiased highly accelerated stress test (uHAST), temperature cycling (TC) test (−40∼150°C) for 1,000 cycles, high temperature storage (HTS) test at 200°C for 1,000hrs and power cycling test (PCT) ($Delta mathrm{T}=150^{circ}mathrm{C}$) for 50,000 cycles. Failure analysis has been conducted for the failed samples.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127212206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00233
Shenghua Huang, Yangming Liu, Ning Ye, Bobby H. Yang
In this paper, dynamic wire sweep in a package during molding is analyzed with Fluid Structure Interaction (FSI) modeling, as well as an experimental validation. Wire bonding (WB) is widely used in integrated circuit (IC) packaging, connecting between chips and substrate. Subsequent molding fluid flow with a certain viscosity and with a certain speed perpendicular to wire curve easily sweeps wires, leading to potential electrical failure. Wires are as thin as tens of micrometers to enable more input-output on a limited chip area. Compared to tens of millimeters in package scale, hundreds of wires are not feasible to model in a package model due to meshing limit. This paper uses an overall flow model considering non-Newton fluid characteristics, from which fluid velocity field is taken as boundary of wire submodel. Overall model contains compound curing kinetic property to capture epoxy reaction during flow because epoxy gelation time is not long. The submodel considers solid-fluid coupling with FSI, as well as thermoset material property, therefore, narrow gap filling around wires and chips could be evaluated. Experimental wire sweep shows consistency with FSI submodel, while non-FSI method could not capture wire sweep in narrow tunnel of compression molding. Curing thermoset material also prevents wires from recovering back elastically. Factors such as wire size, speed, and wire distance are simulated for package design. Results show wire-to-wire distance couples with wire size and impacts on sweep, which could be optimized at design stage with FSI simulation. Small distance may introduce filling issue as molding fluid contains fillers. Front wire may not be able to protect its back wires if their distance is too long. Thicker wire, lower wire loop, and lower inlet speed would help to minimize wire sweep.
{"title":"Fluid Structure Interaction Modeling for Dynamic Wire Sweep","authors":"Shenghua Huang, Yangming Liu, Ning Ye, Bobby H. Yang","doi":"10.1109/ECTC32696.2021.00233","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00233","url":null,"abstract":"In this paper, dynamic wire sweep in a package during molding is analyzed with Fluid Structure Interaction (FSI) modeling, as well as an experimental validation. Wire bonding (WB) is widely used in integrated circuit (IC) packaging, connecting between chips and substrate. Subsequent molding fluid flow with a certain viscosity and with a certain speed perpendicular to wire curve easily sweeps wires, leading to potential electrical failure. Wires are as thin as tens of micrometers to enable more input-output on a limited chip area. Compared to tens of millimeters in package scale, hundreds of wires are not feasible to model in a package model due to meshing limit. This paper uses an overall flow model considering non-Newton fluid characteristics, from which fluid velocity field is taken as boundary of wire submodel. Overall model contains compound curing kinetic property to capture epoxy reaction during flow because epoxy gelation time is not long. The submodel considers solid-fluid coupling with FSI, as well as thermoset material property, therefore, narrow gap filling around wires and chips could be evaluated. Experimental wire sweep shows consistency with FSI submodel, while non-FSI method could not capture wire sweep in narrow tunnel of compression molding. Curing thermoset material also prevents wires from recovering back elastically. Factors such as wire size, speed, and wire distance are simulated for package design. Results show wire-to-wire distance couples with wire size and impacts on sweep, which could be optimized at design stage with FSI simulation. Small distance may introduce filling issue as molding fluid contains fillers. Front wire may not be able to protect its back wires if their distance is too long. Thicker wire, lower wire loop, and lower inlet speed would help to minimize wire sweep.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00318
A. Garnier, L. Castagné, F. Greco, T. Guillemet, L. Marechal, Mehdy Neffati, R. Franiatte, P. Coudrain, S. Piotrowicz, G. Simon
This paper deals with the packaging of two III-V chips combined to form a System-in-Package (SiP) for RF base transceiver station applications. The first die consists of a high-power amplifier (HPA) and a switch made on GaN-on-SiC. The second one features a low-noise amplifier (LNA) and a driver built on GaAs. Both chips bring together the best of each substrate technology, namely high RF and power performances of GaN, and low-noise capability of GaAs. The SiP was built using fan-out wafer-level packaging (FOWLP) in chip-first face-down configuration. The gap between the chips is as low as $mathrm{100} mumathrm{m}$. Electrical routing is secured by redistribution layer (RDL) and balls for flip-chip assembly on the PCB. Thermal dissipation has to be managed opposite to the PCB to avoid a too complex PCB design. It is managed by directly contacting the HPA backside with a Cu-liner acting as a heat spreader. This is achieved by opening the molding compound using laser ablation, and subsequently plating Cu on the SiP backside. The SiP has a final size of $mathrm{4}times mathrm{4}times mathrm{0}.mathrm{35} text{mm}^{mathrm{3}}$, which eventually aims at fitting into the meshing size imposed by an active antenna array operating at 28 GHz. This paper addresses GaN and GaAs chips specific features which have an impact for the FOWLP process flow: low thickness ($sim mathrm{100} mu mathrm{m}$) relative to the targeted $mathrm{350} mumathrm{m}$-thick molding compound; chips backside coated with Au which shall not be removed; chip frontside with a relatively high topology (almost $mathrm{20} mumathrm{m}$). Signal losses were measured in an SiP-like environment at 0.1 dB/mm, 0.2 dB/mm and 0.4 dB/mm respectively at 30 GHz, 40 GHz and 60 GHz. These results are promising in anticipation of the SiP final testing.
{"title":"System in package embedding III-V chips by fan-out wafer-level packaging for RF applications","authors":"A. Garnier, L. Castagné, F. Greco, T. Guillemet, L. Marechal, Mehdy Neffati, R. Franiatte, P. Coudrain, S. Piotrowicz, G. Simon","doi":"10.1109/ECTC32696.2021.00318","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00318","url":null,"abstract":"This paper deals with the packaging of two III-V chips combined to form a System-in-Package (SiP) for RF base transceiver station applications. The first die consists of a high-power amplifier (HPA) and a switch made on GaN-on-SiC. The second one features a low-noise amplifier (LNA) and a driver built on GaAs. Both chips bring together the best of each substrate technology, namely high RF and power performances of GaN, and low-noise capability of GaAs. The SiP was built using fan-out wafer-level packaging (FOWLP) in chip-first face-down configuration. The gap between the chips is as low as $mathrm{100} mumathrm{m}$. Electrical routing is secured by redistribution layer (RDL) and balls for flip-chip assembly on the PCB. Thermal dissipation has to be managed opposite to the PCB to avoid a too complex PCB design. It is managed by directly contacting the HPA backside with a Cu-liner acting as a heat spreader. This is achieved by opening the molding compound using laser ablation, and subsequently plating Cu on the SiP backside. The SiP has a final size of $mathrm{4}times mathrm{4}times mathrm{0}.mathrm{35} text{mm}^{mathrm{3}}$, which eventually aims at fitting into the meshing size imposed by an active antenna array operating at 28 GHz. This paper addresses GaN and GaAs chips specific features which have an impact for the FOWLP process flow: low thickness ($sim mathrm{100} mu mathrm{m}$) relative to the targeted $mathrm{350} mumathrm{m}$-thick molding compound; chips backside coated with Au which shall not be removed; chip frontside with a relatively high topology (almost $mathrm{20} mumathrm{m}$). Signal losses were measured in an SiP-like environment at 0.1 dB/mm, 0.2 dB/mm and 0.4 dB/mm respectively at 30 GHz, 40 GHz and 60 GHz. These results are promising in anticipation of the SiP final testing.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124943345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00290
Ashish Gupta, Anant Chopra
This paper illustrates the signal integrity (SI) performance enhancement in an LPDDR5 system running at 6400 Mbps through the Data Bit Inversion (DBI) feature available in the controller. To demonstrate the abovementioned phenomenon, an SIPI co-simulation is performed to estimate the link performance. For SI, the eye margins for one byte and its corresponding DBI pin in an LPDDR5 channel are simulated. The eye margins are evaluated with and without DBI-compliant versions of the Peak Distortion Analysis (PDA) patterns and are statistically extrapolated to reflect a bit error rate (BER) of 10−16. Upon comparing BER-16 eye margins for the DBI-compliant bit patterns to the original patterns, a significant improvement is observed. The eye height shows 14.8% improvement and the eye width increases by 8.3%.
{"title":"Impact of DBI Feature on Peak Distortion Analysis of LPDDR5 at 6400Mbps","authors":"Ashish Gupta, Anant Chopra","doi":"10.1109/ECTC32696.2021.00290","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00290","url":null,"abstract":"This paper illustrates the signal integrity (SI) performance enhancement in an LPDDR5 system running at 6400 Mbps through the Data Bit Inversion (DBI) feature available in the controller. To demonstrate the abovementioned phenomenon, an SIPI co-simulation is performed to estimate the link performance. For SI, the eye margins for one byte and its corresponding DBI pin in an LPDDR5 channel are simulated. The eye margins are evaluated with and without DBI-compliant versions of the Peak Distortion Analysis (PDA) patterns and are statistically extrapolated to reflect a bit error rate (BER) of 10−16. Upon comparing BER-16 eye margins for the DBI-compliant bit patterns to the original patterns, a significant improvement is observed. The eye height shows 14.8% improvement and the eye width increases by 8.3%.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00335
E. Ouyang, Yonghyuk Jeong, JaeMyong Kim, Jaepil Kim, O. Kwon, M. Liu, Susan Lin, Jenn An Wang, Anthony Yang, Eric Yang
System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing parameters and processes [1], [2]. Previous research on the warpage primarily focused only on the SiP module unit, while the consideration of strip warpage as a function of manufacturing processes has not typically been studied theoretically and experimentally. In this paper, the impact of manufacturing processes, mainly the compression molding process, on the warpage is investigated experimentally and numerically. To better understand the advantages of compression molding, we will also compare compression molding with transfer molding using a computer simulation. The paper will point out the pros and cons of these two different manufacturing processes.
{"title":"Warpage of Compression Molded SiP Strips","authors":"E. Ouyang, Yonghyuk Jeong, JaeMyong Kim, Jaepil Kim, O. Kwon, M. Liu, Susan Lin, Jenn An Wang, Anthony Yang, Eric Yang","doi":"10.1109/ECTC32696.2021.00335","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00335","url":null,"abstract":"System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing parameters and processes [1], [2]. Previous research on the warpage primarily focused only on the SiP module unit, while the consideration of strip warpage as a function of manufacturing processes has not typically been studied theoretically and experimentally. In this paper, the impact of manufacturing processes, mainly the compression molding process, on the warpage is investigated experimentally and numerically. To better understand the advantages of compression molding, we will also compare compression molding with transfer molding using a computer simulation. The paper will point out the pros and cons of these two different manufacturing processes.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123302962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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