Verification of digital circuits based on formal semantics of a hardware description language

M. Mutz
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引用次数: 1

Abstract

The author presents basic concepts of defining semantics of the hardware description language VIOLA based on higher-order logic (HOL). The verification procedures of the hardware verification system VERENA are based on transformations of VIOLA terms. The correctness of these transformation steps can be formally verified based on the HOL semantics of the related VIOLA terms. As a mechanical tool, the HOL prove assistant is used. Basic concepts of a special verification system for the formal verification of digital circuits are presented. HOL serves as the formalism to define the underlying theory.<>
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基于硬件描述语言形式语义的数字电路验证
提出了基于高阶逻辑(HOL)的硬件描述语言VIOLA语义定义的基本概念。硬件验证系统VERENA的验证过程是基于VIOLA项的变换。可以根据相关VIOLA术语的HOL语义正式验证这些转换步骤的正确性。作为一种机械工具,使用HOL证明助手。介绍了数字电路形式化验证专用验证系统的基本概念。HOL作为定义基础理论的形式主义。
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