{"title":"Revisiting shift register realization for ease of test generation and testing","authors":"S. Toida","doi":"10.1109/VTEST.1993.313333","DOIUrl":null,"url":null,"abstract":"The shift register realization of sequential circuits is reexamined. Though the shift register realization requires no extra circuits for scan, and shortens test application time, it in general requires many memory elements. This paper presents a method to reduce the number of memory elements in a shift register realization.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"119 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The shift register realization of sequential circuits is reexamined. Though the shift register realization requires no extra circuits for scan, and shortens test application time, it in general requires many memory elements. This paper presents a method to reduce the number of memory elements in a shift register realization.<>
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