Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313333
S. Toida
The shift register realization of sequential circuits is reexamined. Though the shift register realization requires no extra circuits for scan, and shortens test application time, it in general requires many memory elements. This paper presents a method to reduce the number of memory elements in a shift register realization.<>
{"title":"Revisiting shift register realization for ease of test generation and testing","authors":"S. Toida","doi":"10.1109/VTEST.1993.313333","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313333","url":null,"abstract":"The shift register realization of sequential circuits is reexamined. Though the shift register realization requires no extra circuits for scan, and shortens test application time, it in general requires many memory elements. This paper presents a method to reduce the number of memory elements in a shift register realization.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115598318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313332
M. Jamoussi, B. Kaminska
An approach of a functional-level testability evaluation, based on controllability and observability measures (c.o.m.), is proposed. Using Rutman's system model, ordinary applied at the gate level, c.o.m are extended to the data-path level, to permit incorporation of testability constraints in the high-level synthesis stage. The approach of computing these c.o.m. is based on the reduced ordered binary decision diagram (ROBDD) circuit representation. It is shown how to identify untestable parts of a data path and how to evaluate its test cost. The insertion of a two-variable multiplexor, as a structural modification in the data path, is suggested to improve the c.o.m., and so, the test cost. To evaluate the impact of this transformation on the data-path testability, an objective function is proposed, appropriate for high-level synthesis.<>
{"title":"Controllability and observability measures for functional-level testability evaluation","authors":"M. Jamoussi, B. Kaminska","doi":"10.1109/VTEST.1993.313332","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313332","url":null,"abstract":"An approach of a functional-level testability evaluation, based on controllability and observability measures (c.o.m.), is proposed. Using Rutman's system model, ordinary applied at the gate level, c.o.m are extended to the data-path level, to permit incorporation of testability constraints in the high-level synthesis stage. The approach of computing these c.o.m. is based on the reduced ordered binary decision diagram (ROBDD) circuit representation. It is shown how to identify untestable parts of a data path and how to evaluate its test cost. The insertion of a two-variable multiplexor, as a structural modification in the data path, is suggested to improve the c.o.m., and so, the test cost. To evaluate the impact of this transformation on the data-path testability, an objective function is proposed, appropriate for high-level synthesis.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122065823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313326
H. Abujbara, S. Al-Arian
A new fault model is proposed which accounts for both degrading and catastrophic fault types, which exist in WSI/VLSI designs. Fault degrading is the result of a defect mechanism which has no effect on the logical behavior of the circuit, but rather causes performance degradation to the circuit. This degradation is manifested in poor signal propagation delays, and weak noise immunity. However, there are no testing techniques and no fault models that are capable of handling the testing of the degrading fault by using digital fault simulation. A defect model that is capable of mapping degrading defects syndrome into a Boolean behavior (syndrome) would make it possible to use higher speed digital fault simulation techniques, rather than analog parametric testing. This approach for testing is more reliable and would cover both degrading and fatal (catastrophic) faults in the system.<>
{"title":"Degrading fault model for WSI interconnection lines","authors":"H. Abujbara, S. Al-Arian","doi":"10.1109/VTEST.1993.313326","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313326","url":null,"abstract":"A new fault model is proposed which accounts for both degrading and catastrophic fault types, which exist in WSI/VLSI designs. Fault degrading is the result of a defect mechanism which has no effect on the logical behavior of the circuit, but rather causes performance degradation to the circuit. This degradation is manifested in poor signal propagation delays, and weak noise immunity. However, there are no testing techniques and no fault models that are capable of handling the testing of the degrading fault by using digital fault simulation. A defect model that is capable of mapping degrading defects syndrome into a Boolean behavior (syndrome) would make it possible to use higher speed digital fault simulation techniques, rather than analog parametric testing. This approach for testing is more reliable and would cover both degrading and fatal (catastrophic) faults in the system.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"11 Suppl 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128163217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313371
Z. Hasan, M. Ciesielski
Presents a method to functionally verify a network of interacting finite state machines (FSMs) at any level of abstraction. The verification tool developed can verify the FSM network at various stages of the synthesis process. It can verify the result of FSM decomposition both in the symbolic and binary-coded form. The tool has various options to help the designer in the synthesis of a decomposed sequential machine system. It can generate the decomposed submachines for a given decomposition from the prototype specification. It can also be used to simulate the network. An efficient enumeration-simulation method is used to traverse the state transition graph of the prototype machine in a depth first fashion. The algorithm can be used to verify the decomposed system even if the decomposition information is not known, thus allowing it to verify any FSM network.<>
{"title":"Functional verification and simulation of FSM networks","authors":"Z. Hasan, M. Ciesielski","doi":"10.1109/VTEST.1993.313371","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313371","url":null,"abstract":"Presents a method to functionally verify a network of interacting finite state machines (FSMs) at any level of abstraction. The verification tool developed can verify the FSM network at various stages of the synthesis process. It can verify the result of FSM decomposition both in the symbolic and binary-coded form. The tool has various options to help the designer in the synthesis of a decomposed sequential machine system. It can generate the decomposed submachines for a given decomposition from the prototype specification. It can also be used to simulate the network. An efficient enumeration-simulation method is used to traverse the state transition graph of the prototype machine in a depth first fashion. The algorithm can be used to verify the decomposed system even if the decomposition information is not known, thus allowing it to verify any FSM network.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127845803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313353
Sang-Hoon Song, L. Kinney
Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.<>
{"title":"Incremental test pattern generation","authors":"Sang-Hoon Song, L. Kinney","doi":"10.1109/VTEST.1993.313353","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313353","url":null,"abstract":"Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129481564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313377
J. Alt, U. Mahlstedt
A two-step approach is used to increase the accuracy of fault modeling without sacrificing the efficiency of fault simulation and test pattern generation on the gate level. First, low level faults are mapped onto the gate level and a data base with gate level faults is created. In a second step, fault simulation is performed using this data base. A gate level fault simulator has been modified to perform the simulations. This paper describes the first step and presents a method which maps low level faults onto gate level faults. Existing gate level fault models are extended and new gate level fault models are introduced. In order to demonstrate the feasibility of the approach electrical level shorts and opens have been mapped onto gate level faults for two typical CMOS libraries. For these libraries all shorts and opens can be described accurately by gate level faults.<>
{"title":"Simulation of non-classical faults on the gate level-fault modeling","authors":"J. Alt, U. Mahlstedt","doi":"10.1109/VTEST.1993.313377","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313377","url":null,"abstract":"A two-step approach is used to increase the accuracy of fault modeling without sacrificing the efficiency of fault simulation and test pattern generation on the gate level. First, low level faults are mapped onto the gate level and a data base with gate level faults is created. In a second step, fault simulation is performed using this data base. A gate level fault simulator has been modified to perform the simulations. This paper describes the first step and presents a method which maps low level faults onto gate level faults. Existing gate level fault models are extended and new gate level fault models are introduced. In order to demonstrate the feasibility of the approach electrical level shorts and opens have been mapped onto gate level faults for two typical CMOS libraries. For these libraries all shorts and opens can be described accurately by gate level faults.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127025495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313320
Yunsheng Lu, R. Dandapani
Sensitivity analysis is used to diagnose hard faults in analog circuits. Necessary and sufficient conditions are given to determine the suitability of a given parameter for diagnosis. It is also shown that if a parameter is not suitable then a functional variation of the parameter may be used for diagnosis.<>
{"title":"Hard faults diagnosis in analog circuits using sensitivity analysis","authors":"Yunsheng Lu, R. Dandapani","doi":"10.1109/VTEST.1993.313320","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313320","url":null,"abstract":"Sensitivity analysis is used to diagnose hard faults in analog circuits. Necessary and sufficient conditions are given to determine the suitability of a given parameter for diagnosis. It is also shown that if a parameter is not suitable then a functional variation of the parameter may be used for diagnosis.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"85 40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313328
H. Al-Asaad, E. Czeck
Presents a novel technique for the design of iterative circuits with concurrent error correction capabilities. The new method is called 'recomputing with partitioning and voting' (RWPV). It uses a combination of hardware and time redundancy to achieve fault tolerance while providing the same error correction capabilities as found in hardware TMR or time redundancy computation. RWPV error correction is obtained with small hardware and time overhead, as compared to over 200% overhead in either hardware or time for TMR or time redundancy.<>
{"title":"Concurrent error correction in iterative circuits by recomputing with partitioning and voting","authors":"H. Al-Asaad, E. Czeck","doi":"10.1109/VTEST.1993.313328","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313328","url":null,"abstract":"Presents a novel technique for the design of iterative circuits with concurrent error correction capabilities. The new method is called 'recomputing with partitioning and voting' (RWPV). It uses a combination of hardware and time redundancy to achieve fault tolerance while providing the same error correction capabilities as found in hardware TMR or time redundancy computation. RWPV error correction is obtained with small hardware and time overhead, as compared to over 200% overhead in either hardware or time for TMR or time redundancy.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122913351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313321
W. Vermeiren, Wolfgang Straube, G. Elst
Presents the application of fault detection observers as used in dynamic systems fault diagnosis to analog circuit testing. It will be shown that the fault detectability performance of fault detection observers is higher than those of optimal test vector generation methods which are based on maximising the differences of directly compared responses from the specification and the unit under test.<>
{"title":"Improvement of analog circuit fault detectability using fault detection observers","authors":"W. Vermeiren, Wolfgang Straube, G. Elst","doi":"10.1109/VTEST.1993.313321","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313321","url":null,"abstract":"Presents the application of fault detection observers as used in dynamic systems fault diagnosis to analog circuit testing. It will be shown that the fault detectability performance of fault detection observers is higher than those of optimal test vector generation methods which are based on maximising the differences of directly compared responses from the specification and the unit under test.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133496615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313303
H. Konuk, T. Larrabee
Presents a sequential test generation method based on Boolean satisfiability. The method produces near-minimal test sizes. The authors discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS-89 benchmark circuits and comparisons with previously published results are presented.<>
{"title":"Explorations of sequential ATPG using Boolean satisfiability","authors":"H. Konuk, T. Larrabee","doi":"10.1109/VTEST.1993.313303","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313303","url":null,"abstract":"Presents a sequential test generation method based on Boolean satisfiability. The method produces near-minimal test sizes. The authors discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS-89 benchmark circuits and comparisons with previously published results are presented.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132353387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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