Testing methodology for VLSI

Abstract

The testing problem may dominate cost and even design time for VLSI. Testing at both the system and chip levels will be addressed, stressing the procedures that could be required for full custom versus array-based approaches . . . To be considered too will be the integration of test capability directly on to the chip, and the interface relationships of the designer, producer and test source . . . The techniques which have been successful for MSI and LSI(path scans-LSSD/auto mated test Pattern generation) are likely to fail or have limited applicability for VLSI . . .On-chip testing strategies (self testing of on-board or other macros) may supercede global strategies, such as LSSD...Other equipment and areas that could be involved include the E-beam, and process evaluation and yield maximization testing which may be more appropriate than go/no-go on-board procedures . . .The role of university and education, related to testing and testability, will also be appraised by the panelists.