A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation

Abstract

A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter (SAR ADC) is presented, including a bootstrapped switch, a charge redistribution digital-to-analog converter(DAC) and a dynamic comparator. A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement. A monotonic capacitor switching technique is adopted to reduce the power consumption during conversion. The design of ADC was based on SMIC 0.18μm CMOS process and consumes 5.4mA at 1.8 V power supply. The SAR ADC exhibits an SNR and SFDR of 60.27dB and 65.58dB, respectively.