STDP Design Trade-offs for FPGA-Based Spiking Neural Networks

Abstract

The rise of popularity of Spiking Neural Networks has resulted in a growing interest for simulating synaptic plasticity. Among the existing choices, Spike-Timing-Dependent Plasticity (STDP) represents a reliable solution whose main weakness consists on its high computational cost. This paper proposes several high-frequency FPGA architectures for the realization of pair-based STDP. It also presents a comparison between these implementations and previous ones, and analyzes the compromise between area utilization and precision. We also suggest a SNN architecture capable of implementing in-board STDP learning. The results show that our proposals achieve high throughput and maximum frequencies starting at 400MHz, with a reasonable area utilization and precision loss. The wide range of presented designs makes this work valuable for the decision-taking process in the design and implementation of large scale SNN with different area and precision requirements.