Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2)

Abstract

At-speed memory test demands increasing address rates from ATE bit maps. Today, the effective address rate is multiplied using multiple costly time-interleaved bit map copies. For the first time, address permutation is investigated for memory test in an attempt to multiply the address rate without increasing the overall memory size. However all published schemes create conflicts for some addresses sequences or require too many memories. This paper introduces a novel address partitioning scheme for arbitrarily few memories M = 2mu at the expense of an increased buffer per memory. For relevant address sequences which are based on powers of two, analytical considerations and exhaustive simulations prove that the effective address rate is increased by a factor of M , with zero memory size overhead.