Hardware implementation of 128-bit symmetric cipher SEED

Abstract

This paper presents a hardware implementation of SEED, which is a Korean standard 128-bit symmetric block cipher: the target of the design was FPGA, but SEED was designed technology-independently for other applications such as ASIC or core-based designs. Hence in the case of changing the target of design, it is not necessary to modify design or to need minor modification in order to reuse the design. The design consists of round key generation part, F-function part, control part and round process part. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once, except S-Box, and operated sequentially. Therefore the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. Also it was confirmed that the rate of resource usage is about 80% in ALTERA 10 KE. The design was synthesized in SYNOPSYS synthesis tool using ALTERA 10 K library and was simulated in MAX+PLUSII FPGA tool. The SEED design operates in a clock frequency of 5 MHz and uses 145 clocks. So encryption rate is 4.4 Mbps.