{"title":"A low-power, low-noise, and low-cost VGA for second harmonic imaging ultrasound probes","authors":"P. Wang, T. Ytterdal, T. Halvorsrod","doi":"10.1109/BioCAS.2013.6679702","DOIUrl":null,"url":null,"abstract":"Since the new generation of ultrasound imaging probes will integrate thousands of receive and transmit channels into a single probe, the power, noise, and chip cost become the top challenges for the analog front end of ultrasound imaging probes. This paper investigates a low-power, low-noise, and low-cost single-end-ed to differential variable gain amplifier (VGA) for 2-6-MHz second harmonic imaging ultrasound probes in a 0.18μm CMOS technology. The proposed VGA has two stages. The first stage is an inverter-based voltage sampling switched-capacitor VGA (SC-VGA) with a 6b binary-weighted gain control, and the second stage is a 4b thermometer continuous-time amplifier with tunable gain that implements the single-end to differential conversion. Power consumption and noise are highly improved by adopting an inverter to replace the operational trans-conductance amplifier (OTA) that is commonly employed in traditional SC-VGAs. Flicker noise and DC offset are canceled out by using an auto-zeroing technique. While the small layout size is achieved not only by adopting a dividing capacitor which separates the 6b binary-weighted capacitor (CAP) array between the upper 3b and lower 3b to decrease the capacitance spread in the first stage, but also by employing a common-source amplifier as a single-ended to differential converter instead of the SC-amplifier to avoid the CAP arrays. The proposed VGA has a total gain range from -9dB to 22dB. The power consumption for the core analog circuitry is 140μA at 1V supply voltage. The input referred noise is 8nV/√Hz at the center frequency of 4MHz, and the second harmonic distortion (HD2) is -61dB at a 400mV peak to peak output swing with a 30MHz sampling frequency. The layout size is 109μm×164μm.","PeriodicalId":344317,"journal":{"name":"2013 IEEE Biomedical Circuits and Systems Conference (BioCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Biomedical Circuits and Systems Conference (BioCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BioCAS.2013.6679702","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Since the new generation of ultrasound imaging probes will integrate thousands of receive and transmit channels into a single probe, the power, noise, and chip cost become the top challenges for the analog front end of ultrasound imaging probes. This paper investigates a low-power, low-noise, and low-cost single-end-ed to differential variable gain amplifier (VGA) for 2-6-MHz second harmonic imaging ultrasound probes in a 0.18μm CMOS technology. The proposed VGA has two stages. The first stage is an inverter-based voltage sampling switched-capacitor VGA (SC-VGA) with a 6b binary-weighted gain control, and the second stage is a 4b thermometer continuous-time amplifier with tunable gain that implements the single-end to differential conversion. Power consumption and noise are highly improved by adopting an inverter to replace the operational trans-conductance amplifier (OTA) that is commonly employed in traditional SC-VGAs. Flicker noise and DC offset are canceled out by using an auto-zeroing technique. While the small layout size is achieved not only by adopting a dividing capacitor which separates the 6b binary-weighted capacitor (CAP) array between the upper 3b and lower 3b to decrease the capacitance spread in the first stage, but also by employing a common-source amplifier as a single-ended to differential converter instead of the SC-amplifier to avoid the CAP arrays. The proposed VGA has a total gain range from -9dB to 22dB. The power consumption for the core analog circuitry is 140μA at 1V supply voltage. The input referred noise is 8nV/√Hz at the center frequency of 4MHz, and the second harmonic distortion (HD2) is -61dB at a 400mV peak to peak output swing with a 30MHz sampling frequency. The layout size is 109μm×164μm.