The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era

Abstract

Increase of the process variability with aggressive technology scaling causes many productivity issues in VLSI manufacturing. Analysis about the relationship between process variability and failure has been performed to specify guidelines in both technology and design aspects for yield optimization. By applying the proposed methodology, the core scheme and the operating voltage of the 200 MHz SRAM were determined to secure the immunity to operational failures. In DFM point of view, the statistical circuit analysis for failure characteristics is indispensable to guarantee an optimal yield in manufacturing.