{"title":"Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories","authors":"G. Traversi, F. Canio, V. Liberali, A. Stabile","doi":"10.1109/MOCAST.2017.7937618","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a LVDS input/output interface circuit for the next generation of Associative Memory (AM) chip. The bandwidth of Associative Memories is a critical aspect that needs to be addressed in order to increase the number of comparisons per second. Our aim is to transfer parallel buses at 500 MHz. Since a large number of receivers/drivers will be included in the AM chip, power consumption of the circuits has been taken into account. The design discussed in this work has been submitted for fabrication in December 2016 in a 28 nm CMOS technology.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOCAST.2017.7937618","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper presents the design of a LVDS input/output interface circuit for the next generation of Associative Memory (AM) chip. The bandwidth of Associative Memories is a critical aspect that needs to be addressed in order to increase the number of comparisons per second. Our aim is to transfer parallel buses at 500 MHz. Since a large number of receivers/drivers will be included in the AM chip, power consumption of the circuits has been taken into account. The design discussed in this work has been submitted for fabrication in December 2016 in a 28 nm CMOS technology.
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