A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry

Abstract

We propose an enhanced high-density 6T-SRAM bitcell with multi-Vt asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks. Modified mask structure contributes to reduce the number of halo implant dose masks and achieves dense 0.37 μm2 6T-SRAM bitcell without any area overhead, shrinking to a half size of our previous work. 4-Mbit SRAM test chips are fabricated using 45-nm bulk CMOS technology. Combining with write assist circuitry, the Vmin is reduced by 50 mV and standby leakage by 53%.