Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523655
Ahish Mysore Somashekar, S. Tragoudas
A boolean satisfiability based approach capable of identifying the location of embedded segments with small delay defects, arising due to process variations, is proposed. Furthermore, a novel algorithmic framework is presented to derive swift solutions for the generated conjunctive normal form. To our knowledge, this is the first approach which guarantees that one of the solutions describes the actual defective configurations. Experimental analysis on ISCAS and ITC benchmark suites show that the proposed approach is highly scalable and identifies the location of multiple delay defects.
{"title":"Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements","authors":"Ahish Mysore Somashekar, S. Tragoudas","doi":"10.1109/ISQED.2013.6523655","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523655","url":null,"abstract":"A boolean satisfiability based approach capable of identifying the location of embedded segments with small delay defects, arising due to process variations, is proposed. Furthermore, a novel algorithmic framework is presented to derive swift solutions for the generated conjunctive normal form. To our knowledge, this is the first approach which guarantees that one of the solutions describes the actual defective configurations. Experimental analysis on ISCAS and ITC benchmark suites show that the proposed approach is highly scalable and identifies the location of multiple delay defects.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115471178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523668
R. Krishnan, Wei Wu, Fang Gong, Lei He
Maximum entropy (MAXENT) is a powerful and flexible method for estimating the arbitrary probabilistic distribution of a stochastic variable with moment constraints. However, modeling the stochastic behavior of analog/mixed-signal (AMS) circuits using MAXENT is still unknown. In this paper, we present a MAXENT based approach to efficiently model the arbitrary behavioral distribution of AMS circuits with high accuracy. The exact behavioral distribution can be approximated by a product of exponential functions with different Lagrangian multipliers. The closest approximation can be obtained by maximizing Shannon's information entropy subject to moment constraints, leading to a nonlinear system. Classic Newton's method is used to solve the nonlinear system for the Lagrangian multipliers, which can further recover the arbitrary behavioral distribution of AMS circuits. Extensive experiments on different circuits demonstrate that the proposed MAXENT based approach offers better stability and improves the accuracy up to 110% when compared to previous AWE-based moment matching approaches, and offers up to 592x speedup when compared to Monte Carlo method.
{"title":"Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy","authors":"R. Krishnan, Wei Wu, Fang Gong, Lei He","doi":"10.1109/ISQED.2013.6523668","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523668","url":null,"abstract":"Maximum entropy (MAXENT) is a powerful and flexible method for estimating the arbitrary probabilistic distribution of a stochastic variable with moment constraints. However, modeling the stochastic behavior of analog/mixed-signal (AMS) circuits using MAXENT is still unknown. In this paper, we present a MAXENT based approach to efficiently model the arbitrary behavioral distribution of AMS circuits with high accuracy. The exact behavioral distribution can be approximated by a product of exponential functions with different Lagrangian multipliers. The closest approximation can be obtained by maximizing Shannon's information entropy subject to moment constraints, leading to a nonlinear system. Classic Newton's method is used to solve the nonlinear system for the Lagrangian multipliers, which can further recover the arbitrary behavioral distribution of AMS circuits. Extensive experiments on different circuits demonstrate that the proposed MAXENT based approach offers better stability and improves the accuracy up to 110% when compared to previous AWE-based moment matching approaches, and offers up to 592x speedup when compared to Monte Carlo method.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"140 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123144127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523648
K. Nii, M. Yabuuchi, H. Fujiwara, Y. Tsukamoto, Y. Ishii, T. Matsumura, Y. Matsuda
We propose an enhanced high-density 6T-SRAM bitcell with multi-Vt asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks. Modified mask structure contributes to reduce the number of halo implant dose masks and achieves dense 0.37 μm2 6T-SRAM bitcell without any area overhead, shrinking to a half size of our previous work. 4-Mbit SRAM test chips are fabricated using 45-nm bulk CMOS technology. Combining with write assist circuitry, the Vmin is reduced by 50 mV and standby leakage by 53%.
{"title":"A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry","authors":"K. Nii, M. Yabuuchi, H. Fujiwara, Y. Tsukamoto, Y. Ishii, T. Matsumura, Y. Matsuda","doi":"10.1109/ISQED.2013.6523648","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523648","url":null,"abstract":"We propose an enhanced high-density 6T-SRAM bitcell with multi-Vt asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks. Modified mask structure contributes to reduce the number of halo implant dose masks and achieves dense 0.37 μm2 6T-SRAM bitcell without any area overhead, shrinking to a half size of our previous work. 4-Mbit SRAM test chips are fabricated using 45-nm bulk CMOS technology. Combining with write assist circuitry, the Vmin is reduced by 50 mV and standby leakage by 53%.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115733886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523656
S. M. Sait, A. Arafeh
New advances in nano-electronics have led to the introduction of CMOL (CMOS/Nano-devices hybrid) circuits which consists of an overlay of a nanowires over a CMOS stack. CMOL circuits can implement a netlist of NOR gates and Inverters using diode-like nanodevices. CMOL has inherently restricted connectivity due to limited nanowires length. Therefore connectivity of the circuit's elements is constrained to be within a certain radius, else an intermediary buffers are required. In this paper we present a Tabu search (TS) algorithm to address cells placement problem in CMOL. The Heuristic is engineered to provide feasible circuit implementations by efficient exploration of search space. Empirical results for ISCAS'89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Results show that in almost all cases, TS exhibits more intelligent search of the solutions subspace, and is able to find better solutions. For all tested benchmarks over 90% reduction in average CPU processing time when compared with best published techniques was obtained.
{"title":"Tabu search based cells placement in nanofabric architectures with restricted connectivity","authors":"S. M. Sait, A. Arafeh","doi":"10.1109/ISQED.2013.6523656","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523656","url":null,"abstract":"New advances in nano-electronics have led to the introduction of CMOL (CMOS/Nano-devices hybrid) circuits which consists of an overlay of a nanowires over a CMOS stack. CMOL circuits can implement a netlist of NOR gates and Inverters using diode-like nanodevices. CMOL has inherently restricted connectivity due to limited nanowires length. Therefore connectivity of the circuit's elements is constrained to be within a certain radius, else an intermediary buffers are required. In this paper we present a Tabu search (TS) algorithm to address cells placement problem in CMOL. The Heuristic is engineered to provide feasible circuit implementations by efficient exploration of search space. Empirical results for ISCAS'89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Results show that in almost all cases, TS exhibits more intelligent search of the solutions subspace, and is able to find better solutions. For all tested benchmarks over 90% reduction in average CPU processing time when compared with best published techniques was obtained.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121250859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523659
S. Koranne
VLSI designs contain very large resistive networks consisting of hundreds of millions (10e11) of resistors. Accurate parasitic extraction and analysis of such large networks is essential in many phases of the VLSI design flow. Existing techniques to analyze large resistive networks using linear solvers, despite recent optimizations, still take prohibitive computation time. In this paper a new technique based on low-distortion embedding to estimate point-to-point effective resistance is presented. Our proposed method employs recently discovered techniques from theoretical computer science to compute an ε-approximate resistance embedding matrix from which effective resistances of all node pairs can be estimated as easily as taking the Euclidean norm of column differences. The proposed method runs in almost linear time (linear in the number of resistors), and the accuracy (ε) is user specified. The method has been implemented and experimental results on large networks containing upto 10e11 nodes are presented. Compared to existing method using sparse linear solvers, our methods are more than 10 times faster on mesh networks and more importantly given a network of n nodes, allow computation of effective resistance between arbitrary node pairs in O(lg(n)) time (lg denotes logarithm to base 2).
{"title":"Analysis of very large resistive networks using low distortion embedding","authors":"S. Koranne","doi":"10.1109/ISQED.2013.6523659","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523659","url":null,"abstract":"VLSI designs contain very large resistive networks consisting of hundreds of millions (10e11) of resistors. Accurate parasitic extraction and analysis of such large networks is essential in many phases of the VLSI design flow. Existing techniques to analyze large resistive networks using linear solvers, despite recent optimizations, still take prohibitive computation time. In this paper a new technique based on low-distortion embedding to estimate point-to-point effective resistance is presented. Our proposed method employs recently discovered techniques from theoretical computer science to compute an ε-approximate resistance embedding matrix from which effective resistances of all node pairs can be estimated as easily as taking the Euclidean norm of column differences. The proposed method runs in almost linear time (linear in the number of resistors), and the accuracy (ε) is user specified. The method has been implemented and experimental results on large networks containing upto 10e11 nodes are presented. Compared to existing method using sparse linear solvers, our methods are more than 10 times faster on mesh networks and more importantly given a network of n nodes, allow computation of effective resistance between arbitrary node pairs in O(lg(n)) time (lg denotes logarithm to base 2).","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124802160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523635
Avijit Dutta, Neil Tuttle, K. Anandh
Engineering change order (ECO)s for FPGA-based designs often require design changes late in the design process in order to correct functional, timing, and/or technological problems. Typically, after an ECO process a small portion of the circuit netlist is changed. To take advantage of the enormous resources and time already spent on place and route flow, it is desirable to maintain similar post-routing delay characteristics to the pre-ECO stage to avoid further expensive design iterations. Most FPGA tools use the variance to their advantage to explore the solution space in the design optimization phase. FPGA companies can afford to run multiple passes and just retain the best solution. The embedded systems companies cannot afford multiple pass compile times especially in ECO situations. Note that the variance reduction technique proposed in this paper is applicable only in the ECO situations and not during design optimization phase where variance plays an advantageous role. Predictability is not just unique to ECO, but success of an ECO is highly dependent on predictability and that's where the proposed approach plays a crucial role. The ECO process may change a small subset of the circuit netlist, which may result in a minor variation in the instance list order seen by the packer. Most packing heuristics, including fast greedy heuristics as well as relatively slower non-greedy heuristics, process the input netlist in a certain order and have varying degrees of dependence on the initial instance order. Even a slight variation may result in a substantially different packing and the subsequent placement and routing results may also change. In the worst case, the post-routing delay may fail timing constraints and require inexpensive design iteration. In this paper, we propose a fast canonical ordering technique that either guarantees a unique instance order if the ECO process caused a change in the initial instance order or minimizes the perturbation to the instance order as seen by the packer stage from any significant ECO-induced change to the initial instance order. This helps in isolating the postpacker place and route flow from netlist changes and drastically reduces the variance in post routing delay. Experimental results demonstrate zero variance against random shuffling of instances before the packer stage (to simulate an ECO scenario). Experimental results for other non-functional or slight functional modifications to the input netlist show greatly reduced post-routing delay variance.
{"title":"Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance","authors":"Avijit Dutta, Neil Tuttle, K. Anandh","doi":"10.1109/ISQED.2013.6523635","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523635","url":null,"abstract":"Engineering change order (ECO)s for FPGA-based designs often require design changes late in the design process in order to correct functional, timing, and/or technological problems. Typically, after an ECO process a small portion of the circuit netlist is changed. To take advantage of the enormous resources and time already spent on place and route flow, it is desirable to maintain similar post-routing delay characteristics to the pre-ECO stage to avoid further expensive design iterations. Most FPGA tools use the variance to their advantage to explore the solution space in the design optimization phase. FPGA companies can afford to run multiple passes and just retain the best solution. The embedded systems companies cannot afford multiple pass compile times especially in ECO situations. Note that the variance reduction technique proposed in this paper is applicable only in the ECO situations and not during design optimization phase where variance plays an advantageous role. Predictability is not just unique to ECO, but success of an ECO is highly dependent on predictability and that's where the proposed approach plays a crucial role. The ECO process may change a small subset of the circuit netlist, which may result in a minor variation in the instance list order seen by the packer. Most packing heuristics, including fast greedy heuristics as well as relatively slower non-greedy heuristics, process the input netlist in a certain order and have varying degrees of dependence on the initial instance order. Even a slight variation may result in a substantially different packing and the subsequent placement and routing results may also change. In the worst case, the post-routing delay may fail timing constraints and require inexpensive design iteration. In this paper, we propose a fast canonical ordering technique that either guarantees a unique instance order if the ECO process caused a change in the initial instance order or minimizes the perturbation to the instance order as seen by the packer stage from any significant ECO-induced change to the initial instance order. This helps in isolating the postpacker place and route flow from netlist changes and drastically reduces the variance in post routing delay. Experimental results demonstrate zero variance against random shuffling of instances before the packer stage (to simulate an ECO scenario). Experimental results for other non-functional or slight functional modifications to the input netlist show greatly reduced post-routing delay variance.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"49 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523662
Noemie Beringuier-Boher, D. Hély, V. Beroulle, J. Damiens, P. Candelier
With the increasing diffusion of multi-purpose systems such as smart phones and set-top boxes, security requirements are becoming as important as power consumption and silicon area constraints in SoCs and ASICs conception. In the same time, the complexity of IPs and the new technology nodes make the security evaluation more difficult. Indeed, predicting how a circuit behaves when pushed beyond its specifications limits is now a harder task. While security concerns in software development and digital hardware design are very well known, analog hardware security issues are not really studied. This paper first introduces the security concerns for analog and mixed circuits and then presents a vulnerability analysis methodology dedicated to them. Using this methodology, the security level of AMS SoC and Analog IP is increased by evaluating objectively its vulnerabilities and selecting appropriated countermeasure in the earliest design steps.
{"title":"Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology","authors":"Noemie Beringuier-Boher, D. Hély, V. Beroulle, J. Damiens, P. Candelier","doi":"10.1109/ISQED.2013.6523662","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523662","url":null,"abstract":"With the increasing diffusion of multi-purpose systems such as smart phones and set-top boxes, security requirements are becoming as important as power consumption and silicon area constraints in SoCs and ASICs conception. In the same time, the complexity of IPs and the new technology nodes make the security evaluation more difficult. Indeed, predicting how a circuit behaves when pushed beyond its specifications limits is now a harder task. While security concerns in software development and digital hardware design are very well known, analog hardware security issues are not really studied. This paper first introduces the security concerns for analog and mixed circuits and then presents a vulnerability analysis methodology dedicated to them. Using this methodology, the security level of AMS SoC and Analog IP is increased by evaluating objectively its vulnerabilities and selecting appropriated countermeasure in the earliest design steps.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114572499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523629
Tsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, S. Ruan
Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, with conventional methods, manual and visual-based check are required to locate pins and tune geometries in layouts, which can be very time consuming and unreliable. Instead, an O(NlogN) via-aware standard cell optimization algorithm is developed. The proposed method considers various redundant via configurations such as double-via and rectangle-via which effectively increase the redundant via insertion rate for both concurrent routing and post-layout optimization. As a result, the proposed scheme not only addresses the problem of a low via1 insertion rate in nanometer regimes, but also demonstrates an efficient automatic layout optimizer for designing standard cells. Compared to the conventional standard library, the proposed method saves considerable design effort and time. Experimental results reveal that the proposed method effectively improves the redundant via1 insertion rate by a total of 26.3%.
{"title":"Configurable redundant via-aware standard cell design considering multi-via mechanism","authors":"Tsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, S. Ruan","doi":"10.1109/ISQED.2013.6523629","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523629","url":null,"abstract":"Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, with conventional methods, manual and visual-based check are required to locate pins and tune geometries in layouts, which can be very time consuming and unreliable. Instead, an O(NlogN) via-aware standard cell optimization algorithm is developed. The proposed method considers various redundant via configurations such as double-via and rectangle-via which effectively increase the redundant via insertion rate for both concurrent routing and post-layout optimization. As a result, the proposed scheme not only addresses the problem of a low via1 insertion rate in nanometer regimes, but also demonstrates an efficient automatic layout optimizer for designing standard cells. Compared to the conventional standard library, the proposed method saves considerable design effort and time. Experimental results reveal that the proposed method effectively improves the redundant via1 insertion rate by a total of 26.3%.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523683
Dheepakkumaran Jayaraman, S. Tragoudas
This paper presents a novel approach to determine the sensitization probability of a non-robustly testable path using probability density functions (PDFs). The proposed approach systematically refines a set of patterns that sensitize the path non-robustly which initial set has been derived with existing methods, and is kept implicitly. Accurate measure of the sensitization probability is obtained fast by avoiding Monte-Carlo. It is shown experimentally that the proposed approach is accurate and much faster than Monte-Carlo, and thus can be used to rank a collection of non-robust paths considering their sensitization characteristics.
{"title":"A method to determine the sensitization probability of a non-robustly testable path","authors":"Dheepakkumaran Jayaraman, S. Tragoudas","doi":"10.1109/ISQED.2013.6523683","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523683","url":null,"abstract":"This paper presents a novel approach to determine the sensitization probability of a non-robustly testable path using probability density functions (PDFs). The proposed approach systematically refines a set of patterns that sensitize the path non-robustly which initial set has been derived with existing methods, and is kept implicitly. Accurate measure of the sensitization probability is obtained fast by avoiding Monte-Carlo. It is shown experimentally that the proposed approach is accurate and much faster than Monte-Carlo, and thus can be used to rank a collection of non-robust paths considering their sensitization characteristics.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121389210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523614
M. Sharad, K. Yogendra, K. Kwon, K. Roy
All Spin Logic (ASL) employs multiple nano-magnets interacting through spin-torque using metallic interconnect. ASL gates, being magneto-metallic, can operate at ultra low terminal voltage of few millivolts, and hence can be exploited for low power computation. Since, nano-magnets can preserve their state upon withdrawal of supply voltage, ASL can be pipelined for higher performance, without insertion of extra latches. However, pipelining requires the use of clocked CMOS transistors, which significantly increase the required supply voltage. In this work we analyse the design of an 8-bit, pipelined ASL multiplier, integrated with CMOS clocking circuitry. We propose a design scheme for 3-D ASL, which involves stacking of multiple ASL layers that are clocked using the same CMOS transistors. Stacking of N ASL layers using the proposed scheme can enhance the power saving as well as area density by factor of N. The proposed design scheme for magneto-metallic computational blocks can achieve more than two order of magnitude higher density and 10x lower power consumption as compared to 15nm CMOS design.
{"title":"Design of ultra high density and low power computational blocks using nano-magnets","authors":"M. Sharad, K. Yogendra, K. Kwon, K. Roy","doi":"10.1109/ISQED.2013.6523614","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523614","url":null,"abstract":"All Spin Logic (ASL) employs multiple nano-magnets interacting through spin-torque using metallic interconnect. ASL gates, being magneto-metallic, can operate at ultra low terminal voltage of few millivolts, and hence can be exploited for low power computation. Since, nano-magnets can preserve their state upon withdrawal of supply voltage, ASL can be pipelined for higher performance, without insertion of extra latches. However, pipelining requires the use of clocked CMOS transistors, which significantly increase the required supply voltage. In this work we analyse the design of an 8-bit, pipelined ASL multiplier, integrated with CMOS clocking circuitry. We propose a design scheme for 3-D ASL, which involves stacking of multiple ASL layers that are clocked using the same CMOS transistors. Stacking of N ASL layers using the proposed scheme can enhance the power saving as well as area density by factor of N. The proposed design scheme for magneto-metallic computational blocks can achieve more than two order of magnitude higher density and 10x lower power consumption as compared to 15nm CMOS design.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126425480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：