Low-power voltage multiplier synthesis tool for preliminary topology identification

Abstract

This paper introduces a synthesis tool designed for low-power voltage multipliers. Voltage multipliers are rectifiers employed to generate a constant output voltage, which exceeds the peak-to-peak amplitude voltage of the input signal. At low power levels the attained performance of conventional voltage multipliers is strictly related to the transistor threshold voltage in the multiplication chain, which, at low voltage levels (tens of mV), are operated primarily in the subthreshold region or in cutoff mode. To improve the power conversion efficiency of voltage multipliers at low power levels, this paper introduces a novel passive threshold compensation technique to enhance the transistor conductivity, providing a static bias voltage at the gate of the transistors. Furthermore, a CAD oriented synthesis tool for the presented threshold compensation technique is proposed. The synthesis tool gives a preliminary indication on the rectifier topology (number of stages and compensation order) given target environmental conditions, target output performance, and adopted components in the rectification chain. The core algorithm is based trial and error simulator for the simplified rectifier model, which is employed to speed up the computations pertaining the voltage multiplier synthesis.