Novel CMOS and PTL Based Half Subtractor Designs

Abstract

In the wake of stretched need for movable, light weighted and battery wielded devices, diminishing power consumption, increasing area efficiency and increasing speed of the devices are the foremost crucial factors at present. This paper includes proposals for 16T and 8T half subtractor designs and as they are contrasted with the existing 14T half subtractor design. Simulation of the proposed designs are carried out at various supply voltages i.e., 0. 6V, 0.7V and 0. 8V and in different technologies which are 45nm, 32nm and 16nm technologies which indicate that the proposed designs are technology independent as well. Comparative research communicates that the proposed designs perform better and also yield better results with regards to power dissipation and transistor count as well.