Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00058
P. Lahari, S. Yellampalli, R. Vaddi
Accelerator is a hardware that runs along with the processor and executes the key functions much faster than the processor. The Main purpose of the Accelerator is to increase speed. Deep Neural Networks has achieved wide results in the various Machine Learning Applications Such as image, video, text classification and language translation. The purpose of DNN Accelerators is to speed up the most complex Computation i.e., matrix multiplication. Systolic array Based Accelerator seems like multiply Accumulate unit with Systolic Array based multiplication followed by Adder and accumulator. Multiply Accumulate Unit comprises multiplier, adder and Accumulator. Multiplier is designed used systolic array and that output is given as one of the inputs to the adder followed by Accumulator. In this paper general Matrix based Multiply Accumulate Unit is compared with systolic array based Multiply Accumulate Unit using Xilinx ISE 14.5, various parameters like area, delay and speed are compared. Systolic Array based Multiply Accumulate Unit consumes less area of 49%, less delay of 35% and in turn provides high speed when compared with general matrix multiplier-based multiplier Accumulate unit.
加速器是一种与处理器一起运行的硬件，它执行关键功能的速度比处理器快得多。加速器的主要目的是提高速度。深度神经网络在各种机器学习应用中取得了广泛的成果，如图像、视频、文本分类和语言翻译。DNN加速器的目的是加速最复杂的计算，即矩阵乘法。基于收缩数组的加速器看起来就像用基于收缩数组的乘法乘以累加器和累加器。乘法累加单元包括乘法器、加法器和累加器。乘法器是用收缩阵列设计的，输出作为加法器的一个输入，然后是累加器。本文利用Xilinx ISE 14.5对基于一般矩阵的乘法累加单元和基于收缩阵列的乘法累加单元进行了比较，比较了面积、延迟和速度等参数。与一般基于矩阵乘法器的乘法器累积单元相比，基于收缩阵列的乘法器累积单元消耗的面积少49%，延迟少35%，速度高。
{"title":"Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators","authors":"P. Lahari, S. Yellampalli, R. Vaddi","doi":"10.1109/iSES52644.2021.00058","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00058","url":null,"abstract":"Accelerator is a hardware that runs along with the processor and executes the key functions much faster than the processor. The Main purpose of the Accelerator is to increase speed. Deep Neural Networks has achieved wide results in the various Machine Learning Applications Such as image, video, text classification and language translation. The purpose of DNN Accelerators is to speed up the most complex Computation i.e., matrix multiplication. Systolic array Based Accelerator seems like multiply Accumulate unit with Systolic Array based multiplication followed by Adder and accumulator. Multiply Accumulate Unit comprises multiplier, adder and Accumulator. Multiplier is designed used systolic array and that output is given as one of the inputs to the adder followed by Accumulator. In this paper general Matrix based Multiply Accumulate Unit is compared with systolic array based Multiply Accumulate Unit using Xilinx ISE 14.5, various parameters like area, delay and speed are compared. Systolic Array based Multiply Accumulate Unit consumes less area of 49%, less delay of 35% and in turn provides high speed when compared with general matrix multiplier-based multiplier Accumulate unit.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123129644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00079
Aadil Anam, S. Amin, D. Prasad
In this paper, the simulation study and comparative analysis of the proposed novel hybrid Double-Gate Tunnel Field Effect Transistor (DG-TFET) are extensively done with different conventional TFET structures (different semiconductor materials like Si, Ge and SiGe in the source). The novel hybrid DG-TFET improves the electrical performance (like ON current, subthreshold swing (SS), Ion/Ioff) by undercutting the top ultra-shallow source region and by sandwiching the thin Si channel onto it (between the source and gate). By doing so, along with the lateral tunneling junction (like in the conventional DG-TFET), an additional vertical tunneling junction on an ultra-shallow channel (normal to source gate dielectric) is created. The additional top thin Si channel confines the electric field and along with the lateral tunneling like in the conventional TFETs, it also ensures the possible vertical tunneling. The simulation shows significant improvement in the ON current, SS, and Ion/Ioff, etc. of the proposed hybrid DG-TFET compared to the conventional TFETs. Moreover, to optimize the ON state drain current, the simulation study of the proposed novel hybrid DG-TFET with different front gate/source overlapping has been also done in this paper.
{"title":"Simulation study and comparative analysis of proposed novel hybrid DG-TFET with conventional TFETs structures for improved performance","authors":"Aadil Anam, S. Amin, D. Prasad","doi":"10.1109/iSES52644.2021.00079","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00079","url":null,"abstract":"In this paper, the simulation study and comparative analysis of the proposed novel hybrid Double-Gate Tunnel Field Effect Transistor (DG-TFET) are extensively done with different conventional TFET structures (different semiconductor materials like Si, Ge and SiGe in the source). The novel hybrid DG-TFET improves the electrical performance (like ON current, subthreshold swing (SS), Ion/Ioff) by undercutting the top ultra-shallow source region and by sandwiching the thin Si channel onto it (between the source and gate). By doing so, along with the lateral tunneling junction (like in the conventional DG-TFET), an additional vertical tunneling junction on an ultra-shallow channel (normal to source gate dielectric) is created. The additional top thin Si channel confines the electric field and along with the lateral tunneling like in the conventional TFETs, it also ensures the possible vertical tunneling. The simulation shows significant improvement in the ON current, SS, and Ion/Ioff, etc. of the proposed hybrid DG-TFET compared to the conventional TFETs. Moreover, to optimize the ON state drain current, the simulation study of the proposed novel hybrid DG-TFET with different front gate/source overlapping has been also done in this paper.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126657610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00104
Md. Suman Reza, Sujit Biswas, Abdullah Alghamdi, M. Alrizq, A. Bairagi, Mehedi Masud
Justification of authenticity of academic credentials is a very clumsy task from a global perspective. For digital certificates to be widely accepted requires secure verifications of the issuer, credential holders, and secure data sharing. Physical verification and a traditional centralized digital system are entirely viable for the current era. This paper proposes ACC, a blockchain-based Academic Credentials Chain(ACC), for global authenticity verifications and sharing. The proposed system recognizes from a credential who is certifying whom. In the proposed Blockchain network, a decentralized application allows users to store their credentials data privately. The evaluation results in proof of the feasibility, security and exhibits the level of performance.
{"title":"ACC: Blockchain Based Trusted Management of Academic Credentials","authors":"Md. Suman Reza, Sujit Biswas, Abdullah Alghamdi, M. Alrizq, A. Bairagi, Mehedi Masud","doi":"10.1109/iSES52644.2021.00104","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00104","url":null,"abstract":"Justification of authenticity of academic credentials is a very clumsy task from a global perspective. For digital certificates to be widely accepted requires secure verifications of the issuer, credential holders, and secure data sharing. Physical verification and a traditional centralized digital system are entirely viable for the current era. This paper proposes ACC, a blockchain-based Academic Credentials Chain(ACC), for global authenticity verifications and sharing. The proposed system recognizes from a credential who is certifying whom. In the proposed Blockchain network, a decentralized application allows users to store their credentials data privately. The evaluation results in proof of the feasibility, security and exhibits the level of performance.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00103
A. Chandak, N. Ray, Deepak Puthal
A smart home contains smart gadgets which are generating a huge amount of data. The utilization of IoT gadgets in smart homes is constantly expanding and for faster processing of data, appropriate resources will be required. This generated data is passed to the cloud for processing but there may be a delay in the processing of data. Edge devices reside at the edges of smart gadgets and perform quick processing of data. Computation speed can be increased if generated data is classified and assigned to the edge node. The classifier is commonly used in machine learning algorithms. It can also be used in smart city and smart home applications. Data classification helps in decision-making by finding outliers from data. Many algorithms are available for data classification and out of which the rule-based classifier [1] and k-means clustering [2] are the most commonly used classifier. In this paper, we attempted to analyze the performance of the rule-based classifier and k-means clustering based on evaluation parameters viz. average execution time, service latency, and resource utilization. From the simulation results, it is observed that k-means clustering performs better as compared to rule-based classifier.
{"title":"Performance Analysis of Classifier Techniques at the Edge Node","authors":"A. Chandak, N. Ray, Deepak Puthal","doi":"10.1109/iSES52644.2021.00103","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00103","url":null,"abstract":"A smart home contains smart gadgets which are generating a huge amount of data. The utilization of IoT gadgets in smart homes is constantly expanding and for faster processing of data, appropriate resources will be required. This generated data is passed to the cloud for processing but there may be a delay in the processing of data. Edge devices reside at the edges of smart gadgets and perform quick processing of data. Computation speed can be increased if generated data is classified and assigned to the edge node. The classifier is commonly used in machine learning algorithms. It can also be used in smart city and smart home applications. Data classification helps in decision-making by finding outliers from data. Many algorithms are available for data classification and out of which the rule-based classifier [1] and k-means clustering [2] are the most commonly used classifier. In this paper, we attempted to analyze the performance of the rule-based classifier and k-means clustering based on evaluation parameters viz. average execution time, service latency, and resource utilization. From the simulation results, it is observed that k-means clustering performs better as compared to rule-based classifier.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122759443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00034
Dan Wagner, Arslan Munir, M. Neilsen
Experimentation within the field of agronomy relies upon maintaining a controlled operating environment to determine various environmental factors’ effects upon a crop. These experiments are carried out in small growth chambers and can control limited variables such as light, temperature, and humidity. Space is a premium inside the chambers which limits the capacity for additional sensors and other equipment. Field conditions are more complex than a growth chamber, which makes it difficult to analyze the effect of factors in a more realistic scenario. In this paper, we propose a system architecture for a field-based controlled environment for agriculture and experimentation. First, the overall architecture is proposed for integrating a multitude of wired and wireless sensors, different controllers, small unmanned aerial vehicles (UAVs) and unmanned ground vehicles (UGVs), and actuators to assess and maintain environmental variables. Next, each component is detailed for its role and responsibilities within the system. Then, scientific applications of the system are proposed and explored before finally analyzing a case study implementation of the architecture.
{"title":"A Novel System Architecture for Automated Field-Based Tent Systems for Controlled-Environment Agriculture","authors":"Dan Wagner, Arslan Munir, M. Neilsen","doi":"10.1109/iSES52644.2021.00034","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00034","url":null,"abstract":"Experimentation within the field of agronomy relies upon maintaining a controlled operating environment to determine various environmental factors’ effects upon a crop. These experiments are carried out in small growth chambers and can control limited variables such as light, temperature, and humidity. Space is a premium inside the chambers which limits the capacity for additional sensors and other equipment. Field conditions are more complex than a growth chamber, which makes it difficult to analyze the effect of factors in a more realistic scenario. In this paper, we propose a system architecture for a field-based controlled environment for agriculture and experimentation. First, the overall architecture is proposed for integrating a multitude of wired and wireless sensors, different controllers, small unmanned aerial vehicles (UAVs) and unmanned ground vehicles (UGVs), and actuators to assess and maintain environmental variables. Next, each component is detailed for its role and responsibilities within the system. Then, scientific applications of the system are proposed and explored before finally analyzing a case study implementation of the architecture.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126704111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Millions of speech-hearing disabled persons routinely use various signs like hand shapes, movement of hands, lip, and facial expressions to communicate. Indian Sign Language(ISL) is a language that has a large vocabulary of words, which changes from region to region. Generally, there is no dataset publicly available on sequential gestures for ISL. Therefore, the authors have presented the dynamic hand gesture dataset having 33 categories, including months of the year, days of the week, and those used in day-today life. This dataset is collected with a technique called burst shots. To enable speedy evaluation, a smaller subset of the dataset is used with 12 classes represents the months of the year. It is pretty complex because of its signs, and each category contains an average of 5 to 6 gestures per class. The proposed model is designed to work on low-power embedded hardware and this paper also discusses the workflow for the deployment of the particular neural network on embedded hardware. Furthermore, the proposed model is compared with different sequential architectures to find the most suited model for dynamic hand gesture recognition.
{"title":"Dynamic Two Hand Gesture Recognition using CNN-LSTM based networks","authors":"Vaidehi Sharma, Mohita Jaiswal, Abhishek Sharma, Sandeep Saini, Raghuvir Tomar","doi":"10.1109/iSES52644.2021.00059","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00059","url":null,"abstract":"Millions of speech-hearing disabled persons routinely use various signs like hand shapes, movement of hands, lip, and facial expressions to communicate. Indian Sign Language(ISL) is a language that has a large vocabulary of words, which changes from region to region. Generally, there is no dataset publicly available on sequential gestures for ISL. Therefore, the authors have presented the dynamic hand gesture dataset having 33 categories, including months of the year, days of the week, and those used in day-today life. This dataset is collected with a technique called burst shots. To enable speedy evaluation, a smaller subset of the dataset is used with 12 classes represents the months of the year. It is pretty complex because of its signs, and each category contains an average of 5 to 6 gestures per class. The proposed model is designed to work on low-power embedded hardware and this paper also discusses the workflow for the deployment of the particular neural network on embedded hardware. Furthermore, the proposed model is compared with different sequential architectures to find the most suited model for dynamic hand gesture recognition.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114624637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00028
Jyoti Sharma, T. Varma, D. Boolchandani
In phase-locked loop (PLL) systems, the phase frequency detector (PFD) plays a critical role. A PFD compares the two input signals and generates outputs based on the phase difference between them. The input signals in a PFD are the reference signal and the voltage-controlled oscillator (VCO) output signal, while the output signals are the UP and DOWN signals. The VCO regulates its output frequency based on these output signals. If the UP signal is high, the VCO raises its frequency, and if the DOWN signal is high, the VCO lowers its frequency. This paper looked into and assessed a variety of PFD circuits. The effect of several topologies on the performance indicators of the PFD has been examined. Some of the performance parameters of PFDs that are compared in this study are dead zone, power dissipation, noise, and maximum operating frequency.
{"title":"A brief review of the various phase-frequency detector architectures","authors":"Jyoti Sharma, T. Varma, D. Boolchandani","doi":"10.1109/iSES52644.2021.00028","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00028","url":null,"abstract":"In phase-locked loop (PLL) systems, the phase frequency detector (PFD) plays a critical role. A PFD compares the two input signals and generates outputs based on the phase difference between them. The input signals in a PFD are the reference signal and the voltage-controlled oscillator (VCO) output signal, while the output signals are the UP and DOWN signals. The VCO regulates its output frequency based on these output signals. If the UP signal is high, the VCO raises its frequency, and if the DOWN signal is high, the VCO lowers its frequency. This paper looked into and assessed a variety of PFD circuits. The effect of several topologies on the performance indicators of the PFD has been examined. Some of the performance parameters of PFDs that are compared in this study are dead zone, power dissipation, noise, and maximum operating frequency.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121655215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In Internet of Things (IOT) based applications, security is given the highest importance and cryptography plays a major role in maintaining the data safety. Encryption and decryption in cryptography requires a Pseudo random bit generator (PRBG) for key generation. Modified dual coupled linear congruential generator (MDCLCG) based PRBG is the highly efficient PRBG algorithm as it clears a1115 National Institute of Standards and Technology (NIST) tests and has maximum period of 2n for a n-bit design. In this paper, complete design and testing of a 64-bit MDCLCG based PRBG is proposed and it’s implementation on Kintex-7 XC7K160TFBG676-3 field-programmable gate array (FPGA) is presented. Main components of MDCLCG based PRBG includes a Three operand adder, Barrel shifter, Comparator and an Encoder. Further, a High speed area efficient three operand adder (HSAEA) is used to improve performance of the proposed 64-bit MDCLCG architecture. It’s performance is compared with 64-bit MDCLCG designed using three operand Ultra fast adder (UFA) and three operand Carry save adder (CSA) architectures. The post-implementation results of the proposed 64-bit MDCLCG are carried out and from the analysis, it is reported that the proposed 64-bit MDCLCG designed using HSAEA has 25.1%, 9.2% reduction in Area/Maximum frequency $(A/F_{Max})$ value when compared to UFA and CSA based 64-bit MDCLCG architectures respectively. Also, it has 17.7%, 4.4% reduction in Power/Maximum frequency $(P/F_{Max})$ value over UFA and CSA based 64-bit MDCLCG architectures respectively. Moreover, the proposed 64-bit MDCLCG ensures more security than 32-bit MDCLCG proposed in literature as the pseudo random bit sequence has a period of 264 bits instead of 232 bits.
在基于物联网(IOT)的应用中，安全性是最重要的，而密码学在维护数据安全方面起着重要作用。密码学中的加密和解密需要伪随机比特发生器(PRBG)来生成密钥。基于改进的双耦合线性同余发生器(MDCLCG)的PRBG是一种高效的PRBG算法，它通过了美国国家标准与技术研究所(NIST)的1115测试，并且对于n位设计具有2n的最大周期。本文提出了一种基于64位MDCLCG的PRBG的完整设计和测试，并在Kintex-7 XC7K160TFBG676-3现场可编程门阵列(FPGA)上实现。基于MDCLCG的PRBG主要由三操作数加法器、桶移器、比较器和编码器组成。此外，采用高速区域高效三操作数加法器(HSAEA)来提高64位MDCLCG架构的性能。将其性能与采用三操作数超快速加法器(UFA)和三操作数进位保存加法器(CSA)架构设计的64位MDCLCG进行了比较。对所提出的64位MDCLCG进行了实施后的结果分析，结果表明，与基于UFA和基于CSA的64位MDCLCG架构相比，采用HSAEA设计的64位MDCLCG在Area/Maximum frequency $(A/F_{Max})$值上分别降低了25.1%和9.2%。此外，与基于UFA和基于CSA的64位MDCLCG架构相比，它的功率/最大频率$(P/F_{Max})$值分别降低了17.7%和4.4%。此外，由于伪随机位序列的周期为264位而不是232位，因此所提出的64位MDCLCG比文献中提出的32位MDCLCG具有更高的安全性。
{"title":"Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator","authors":"Krishna Sai Tarun Ramapragada, Ajith Kumar Reddy Netla, Pavan Kalyan Chattada, Bhaskar Manickam","doi":"10.1109/iSES52644.2021.00032","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00032","url":null,"abstract":"In Internet of Things (IOT) based applications, security is given the highest importance and cryptography plays a major role in maintaining the data safety. Encryption and decryption in cryptography requires a Pseudo random bit generator (PRBG) for key generation. Modified dual coupled linear congruential generator (MDCLCG) based PRBG is the highly efficient PRBG algorithm as it clears a1115 National Institute of Standards and Technology (NIST) tests and has maximum period of 2n for a n-bit design. In this paper, complete design and testing of a 64-bit MDCLCG based PRBG is proposed and it’s implementation on Kintex-7 XC7K160TFBG676-3 field-programmable gate array (FPGA) is presented. Main components of MDCLCG based PRBG includes a Three operand adder, Barrel shifter, Comparator and an Encoder. Further, a High speed area efficient three operand adder (HSAEA) is used to improve performance of the proposed 64-bit MDCLCG architecture. It’s performance is compared with 64-bit MDCLCG designed using three operand Ultra fast adder (UFA) and three operand Carry save adder (CSA) architectures. The post-implementation results of the proposed 64-bit MDCLCG are carried out and from the analysis, it is reported that the proposed 64-bit MDCLCG designed using HSAEA has 25.1%, 9.2% reduction in Area/Maximum frequency $(A/F_{Max})$ value when compared to UFA and CSA based 64-bit MDCLCG architectures respectively. Also, it has 17.7%, 4.4% reduction in Power/Maximum frequency $(P/F_{Max})$ value over UFA and CSA based 64-bit MDCLCG architectures respectively. Moreover, the proposed 64-bit MDCLCG ensures more security than 32-bit MDCLCG proposed in literature as the pseudo random bit sequence has a period of 264 bits instead of 232 bits.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127669199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00105
G. J. Reddy., G. Kumar, T. Lohitasya, V. S. Nilay, K. Praveen, B. S. Egala, A. K. Pradhan
Globalization has made supply chain business management more complicated over time. The existence of intermediary parties in the supply chain causes major issues like product genuineness, as well as transparency in product quality and quantity information management, etc. Traditional supply chain models depend on intermediaries and also are cloud-based systems. It is very much difficult to track the data state changes across the supply chain’s larger network. Latest technologies such as blockchain and the Internet of Things (IoT) play a critical role in bringing transparency to supply chain management. In this paper, we have proposed FarmersChain, a novel decentralized data-centric smart supply chain management system based on blockchain and IoT technologies. In our proposed system FarmerChain, smart contracts are used to automate digital agreements. It was examined and analyzed on a local testbed to demonstrate its potential. Based on the system analysis and testing, we discovered that the proposed supply chain management is feasible in a real-time environment without the interference of a third party and middleman. It also ensures the product’s quality and quantity information status is accurate, accessible, and transparent.
{"title":"FarmersChain: A Decentralized Farmer Centric Supply Chain Management System Using Blockchain and IoT","authors":"G. J. Reddy., G. Kumar, T. Lohitasya, V. S. Nilay, K. Praveen, B. S. Egala, A. K. Pradhan","doi":"10.1109/iSES52644.2021.00105","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00105","url":null,"abstract":"Globalization has made supply chain business management more complicated over time. The existence of intermediary parties in the supply chain causes major issues like product genuineness, as well as transparency in product quality and quantity information management, etc. Traditional supply chain models depend on intermediaries and also are cloud-based systems. It is very much difficult to track the data state changes across the supply chain’s larger network. Latest technologies such as blockchain and the Internet of Things (IoT) play a critical role in bringing transparency to supply chain management. In this paper, we have proposed FarmersChain, a novel decentralized data-centric smart supply chain management system based on blockchain and IoT technologies. In our proposed system FarmerChain, smart contracts are used to automate digital agreements. It was examined and analyzed on a local testbed to demonstrate its potential. Based on the system analysis and testing, we discovered that the proposed supply chain management is feasible in a real-time environment without the interference of a third party and middleman. It also ensures the product’s quality and quantity information status is accurate, accessible, and transparent.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"51 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132511390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00048
Naitik M. Nakrani, M. Joshi
This paper proposes a multi-stage, neuro-fuzzy architecture for autonomous parallel parking in a complex and dynamic environment. It provides an obstacle avoidance capability for the vehicle during the parking maneuver. Fuzzy controller transforms input information into effective vehicle parking by switching between navigation and parking modules. In order to sense the environment better, a trained neural network is appended as an input pre controller to the central fuzzy controller for obstacle avoidance. To demonstrate the efficacy of the proposed architecture, simulation tests are carried out in the presence of both static and moving obstacles.
{"title":"Neuro-fuzzy based system for autonomous vehicle parking in the dynamic environment","authors":"Naitik M. Nakrani, M. Joshi","doi":"10.1109/iSES52644.2021.00048","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00048","url":null,"abstract":"This paper proposes a multi-stage, neuro-fuzzy architecture for autonomous parallel parking in a complex and dynamic environment. It provides an obstacle avoidance capability for the vehicle during the parking maneuver. Fuzzy controller transforms input information into effective vehicle parking by switching between navigation and parking modules. In order to sense the environment better, a trained neural network is appended as an input pre controller to the central fuzzy controller for obstacle avoidance. To demonstrate the efficacy of the proposed architecture, simulation tests are carried out in the presence of both static and moving obstacles.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131068795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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