{"title":"Hardware reduction for RAM-based Moore FSMs","authors":"M. Kolopienczyk, A. Barkalov, L. Titarenko","doi":"10.1109/HSI.2014.6860485","DOIUrl":null,"url":null,"abstract":"A method is proposed allowing implementing logic circuit of Moore FSM with embedded memory block of FPGA chips. The method is based on replacement some part of the set of logical conditions by additional variables. It results in diminishing for the number of LUTs in the multiplexer used for replacement of logical conditions. An example of proposed design methods application is given.","PeriodicalId":448379,"journal":{"name":"2014 7th International Conference on Human System Interactions (HSI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 7th International Conference on Human System Interactions (HSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HSI.2014.6860485","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A method is proposed allowing implementing logic circuit of Moore FSM with embedded memory block of FPGA chips. The method is based on replacement some part of the set of logical conditions by additional variables. It results in diminishing for the number of LUTs in the multiplexer used for replacement of logical conditions. An example of proposed design methods application is given.
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