Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration

Abstract

Modern computer architectures have an ever-increasing demand for performance, but are constrained in power dissipation and chip area. To tackle these demands, architectures with application-specific accelerators have gained traction in research and industry. While this is a very promising direction, hard-wired accelerators fall short when too many applications need to be supported or flexibility is required. In this paper, we propose an automatic loop detection and hardware acceleration approach for an adaptive reconfigurable processor. Our contribution is Auto-SI, an automated process that transparently and dynamically provides hardware acceleration alongside a general-purpose processor by employing reconfigurable hardware. We detail the benefits of Auto-SI, i.e., transparent and flexible acceleration of unmodified binaries, provide an analysis of the overheads incurred and present an evaluation of our implementation prototype.