RAMSES: a fast memory fault simulator

Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
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引用次数: 84

Abstract

In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N/sup 3/) to O(N/sup 2/), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.
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RAMSES:快速内存故障模拟器
在本文中,我们提出了一种存储器故障模拟器,称为错误筛选随机存取存储器模拟器(RAMSES)。虽然该算法是基于一些已知的内存故障模型设计的,但我们所开发的算法保证了通过添加新的故障描述符而不是修改算法或程序可以很容易地包含新的故障模型。RAMSES将内存故障模拟的时间复杂度从0 (N/sup 3/)提高到O(N/sup 2/),其中N为内存容量,单位为比特。我们的方法只需要少量的额外内存空间。RAMSES仿真结果表明,采用该方法可以显著缩短测试时间。在RAMSES的帮助下,开发了一种高效的面向词记忆测试算法March-CW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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