Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802891
C. Bolchini, L. Pomante, D. Sciuto, F. Salice
This paper proposes a synthesis methodology aimed at improving the concurrent error property of combinational TSC devices. The methodology is based on an iterative application of a structural modification of the device (observability modification) and an evaluation of the impact of such a modification. The quality evaluation is performed by means of a cost function for totally self-checking combinational devices which takes into account different aspects besides the area overhead criterion for comparing different realization strategies. The methodology has been validated on a set of MCNC91 benchmarks.
{"title":"A synthesis methodology aimed at improving the quality of TSC devices","authors":"C. Bolchini, L. Pomante, D. Sciuto, F. Salice","doi":"10.1109/DFTVS.1999.802891","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802891","url":null,"abstract":"This paper proposes a synthesis methodology aimed at improving the concurrent error property of combinational TSC devices. The methodology is based on an iterative application of a structural modification of the device (observability modification) and an evaluation of the impact of such a modification. The quality evaluation is performed by means of a cost function for totally self-checking combinational devices which takes into account different aspects besides the area overhead criterion for comparing different realization strategies. The methodology has been validated on a set of MCNC91 benchmarks.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"472 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122428530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802870
F. Duvivier
In high volume production, it is important to have a fast response time to yield loss mechanisms. This paper presents a way to detect spatial yield loss on wafers. A procedure automatically computes and provides a summary of signatures taking into account all of the processed wafer. This reduces manual manipulation of data, providing a faster response time.
{"title":"Automatic detection of spatial signature on wafermaps in a high volume production","authors":"F. Duvivier","doi":"10.1109/DFTVS.1999.802870","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802870","url":null,"abstract":"In high volume production, it is important to have a fast response time to yield loss mechanisms. This paper presents a way to detect spatial yield loss on wafers. A procedure automatically computes and provides a summary of signatures taking into account all of the processed wafer. This reduces manual manipulation of data, providing a faster response time.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132321376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802895
K. Saowapa, H. Kaneko, E. Fujiwara
This paper presents a class of binary block codes capable of correcting single synchronization error and single reversal error with fewer check bits than the existing codes. This also shows a decoding circuit and analyzes its complexity.
{"title":"Systematic deletion/insertion error correcting codes with random error correction capability","authors":"K. Saowapa, H. Kaneko, E. Fujiwara","doi":"10.1109/DFTVS.1999.802895","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802895","url":null,"abstract":"This paper presents a class of binary block codes capable of correcting single synchronization error and single reversal error with fewer check bits than the existing codes. This also shows a decoding circuit and analyzes its complexity.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"34 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123293322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802907
S. Nakano, N. Kamiura, Y. Hata, N. Matsui
In this paper we discuss the reconfiguration of two-dimensional meshes embedded in hypercubes with link and/or node failures. First, we assume that only the link failures may occur. Our method consists of two stages. The first stage assigns dimensions of hypercube to two directions of mesh so that the losses of rows or columns would be as small as possible. The second stage establishes the mesh communication by assigning the Cartesian product of two Gray code sequences to every node. We generate these sequences with a depth-first search or generic algorithm. This method can be applied to node failures by regarding a faulty node as a node whose links are entirely faulty. Our simulation results show that our method can reconfigure large meshes with short computation time.
{"title":"Reconfiguration of two-dimensional meshes embedded in faulty hypercubes","authors":"S. Nakano, N. Kamiura, Y. Hata, N. Matsui","doi":"10.1109/DFTVS.1999.802907","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802907","url":null,"abstract":"In this paper we discuss the reconfiguration of two-dimensional meshes embedded in hypercubes with link and/or node failures. First, we assume that only the link failures may occur. Our method consists of two stages. The first stage assigns dimensions of hypercube to two directions of mesh so that the losses of rows or columns would be as small as possible. The second stage establishes the mesh communication by assigning the Cartesian product of two Gray code sequences to every node. We generate these sequences with a depth-first search or generic algorithm. This method can be applied to node failures by regarding a faulty node as a node whose links are entirely faulty. Our simulation results show that our method can reconfigure large meshes with short computation time.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131399634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802900
S. D'Angelo, G. Sechi, C. Metra
In this paper we propose a hardware scheme to allow the diagnosis of transient and permanent faults affecting a Triple Modular Redundancy (TMR) system implemented by means of Field Programmable Gate Arrays (FPGAs). Our scheme allows us to easily identify whether a fault affects one of the replicated modules, the voter, or the scheme itself; and whether such a fault is permanent or transient. Our scheme can therefore be used to drive the selection of the most proper recovery technique for each kind of diagnosed fault. It is suitable to be implemented by means of FPGAs, and has been verified to feature self-checking ability with respect to a wide set of possible internal faults belonging to a realistic set.
{"title":"Transient and permanent fault diagnosis for FPGA-based TMR systems","authors":"S. D'Angelo, G. Sechi, C. Metra","doi":"10.1109/DFTVS.1999.802900","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802900","url":null,"abstract":"In this paper we propose a hardware scheme to allow the diagnosis of transient and permanent faults affecting a Triple Modular Redundancy (TMR) system implemented by means of Field Programmable Gate Arrays (FPGAs). Our scheme allows us to easily identify whether a fault affects one of the replicated modules, the voter, or the scheme itself; and whether such a fault is permanent or transient. Our scheme can therefore be used to drive the selection of the most proper recovery technique for each kind of diagnosed fault. It is suitable to be implemented by means of FPGAs, and has been verified to feature self-checking ability with respect to a wide set of possible internal faults belonging to a realistic set.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"414 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114049886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802894
M. Alderighi, S. D'Angelo, G. Sechi, V. Piuri
The paper presents and evaluates the design and the implementation of a self-checking neural system for photon event identification in intensified charge-coupled device detectors. The neural approach reveals more effective than classical algorithmic approaches thanks to its learning through example ability. Implementation is accomplished by SRAM-based FPGAs, which have generated increasing interest in the space community. The adoption of suitable on-line fault detection techniques is illustrated taking into account in a specific way SEU induced faults. The techniques are based on AN coding, particularly 3N coding, which constitutes a reasonable trade-off between circuit complexity and computational delay. Estimations of circuit area overhead and fault coverage are reported.
{"title":"Implementing a self-checking neural system for photon event identification by SRAM-based FPGAs","authors":"M. Alderighi, S. D'Angelo, G. Sechi, V. Piuri","doi":"10.1109/DFTVS.1999.802894","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802894","url":null,"abstract":"The paper presents and evaluates the design and the implementation of a self-checking neural system for photon event identification in intensified charge-coupled device detectors. The neural approach reveals more effective than classical algorithmic approaches thanks to its learning through example ability. Implementation is accomplished by SRAM-based FPGAs, which have generated increasing interest in the space community. The adoption of suitable on-line fault detection techniques is illustrated taking into account in a specific way SEU induced faults. The techniques are based on AN coding, particularly 3N coding, which constitutes a reasonable trade-off between circuit complexity and computational delay. Estimations of circuit area overhead and fault coverage are reported.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115841806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802871
J. Plusquellic, Amy Germida, Zheng Yan
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. In this paper the power supply transient signals from simulation experiments on an 8-bit multiplier are analyzed at multiple test points in both the time and frequency domain. Linear regression analysis is used to separate and identify the signal variations introduced by defects and the variations caused by changes in fabrication process parameters. Defects were introduced into the simulation model by adding material (shorts) or removing material (opens) from the layout. Process parameter fluctuations were modeled by randomly varying transistor and circuit parameters individually and in groups over the range of +/-25% of the nominal parameters. The results of the analysis show that it is possible to distinguish between defect-free devices with injected process variation and defective devices.
{"title":"8-bit multiplier simulation experiments investigating the use of power supply transient signals for the detection of CMOS defects","authors":"J. Plusquellic, Amy Germida, Zheng Yan","doi":"10.1109/DFTVS.1999.802871","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802871","url":null,"abstract":"Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. In this paper the power supply transient signals from simulation experiments on an 8-bit multiplier are analyzed at multiple test points in both the time and frequency domain. Linear regression analysis is used to separate and identify the signal variations introduced by defects and the variations caused by changes in fabrication process parameters. Defects were introduced into the simulation model by adding material (shorts) or removing material (opens) from the layout. Process parameter fluctuations were modeled by randomly varying transistor and circuit parameters individually and in groups over the range of +/-25% of the nominal parameters. The results of the analysis show that it is possible to distinguish between defect-free devices with injected process variation and defective devices.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802897
G. Cardarilli, S. Bertazzoni, M. Salmeri, A. Salsano, P. Marinucci
This paper presents the flow used for the design of a fault-tolerant solid state mass memory (SSMM) based on commercial off the shelf (COTS) 64 Mb DRAMs. The effects of high-energy radiations on these devices are often complex. In particular, in the paper we consider heavy ion and proton induced soft and hard errors in DRAM devices. In our work, these errors are mitigated at system level rather at device level. In fact the mass memory is based on a suitable ECC code that improves its tolerance with respect to errors induced in DRAMs. The definition of a SSMM architecture is very complex since the design has to take into account the radiation environment and the different system constraints. In this paper we presents the methodology, derived from the operational research theory, used to select the codes and the memory architecture, taking into account the different design constraints.
{"title":"Design of fault-tolerant solid state mass memory","authors":"G. Cardarilli, S. Bertazzoni, M. Salmeri, A. Salsano, P. Marinucci","doi":"10.1109/DFTVS.1999.802897","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802897","url":null,"abstract":"This paper presents the flow used for the design of a fault-tolerant solid state mass memory (SSMM) based on commercial off the shelf (COTS) 64 Mb DRAMs. The effects of high-energy radiations on these devices are often complex. In particular, in the paper we consider heavy ion and proton induced soft and hard errors in DRAM devices. In our work, these errors are mitigated at system level rather at device level. In fact the mass memory is based on a suitable ECC code that improves its tolerance with respect to errors induced in DRAMs. The definition of a SSMM architecture is very complex since the design has to take into account the radiation environment and the different system constraints. In this paper we presents the methodology, derived from the operational research theory, used to select the codes and the memory architecture, taking into account the different design constraints.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130898954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802880
Xiaodong Zhang, K. Roy
In order to meet the power and reliability constraints, it is important to reduce average power and peak power during test. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG), which can be used during online testing of large circuits requiring low power dissipation. The LPATPG can be implemented by linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by finding the best initial conditions in the CA cells. Results on ISCAS benchmark circuits show that average power reduction of up to 79.7%, peak power reduction of up to 39.2% and energy reduction of up to 84.4% can be achieved (compared to linear cellular automata) while achieving high fault coverage.
{"title":"Design and synthesis of low power weighted random pattern generator considering peak power reduction","authors":"Xiaodong Zhang, K. Roy","doi":"10.1109/DFTVS.1999.802880","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802880","url":null,"abstract":"In order to meet the power and reliability constraints, it is important to reduce average power and peak power during test. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG), which can be used during online testing of large circuits requiring low power dissipation. The LPATPG can be implemented by linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by finding the best initial conditions in the CA cells. Results on ISCAS benchmark circuits show that average power reduction of up to 79.7%, peak power reduction of up to 39.2% and energy reduction of up to 84.4% can be achieved (compared to linear cellular automata) while achieving high fault coverage.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116440159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802905
A. Doumar, S. Kaneko, Hideo Ito
The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and horse-allocation) are introduced and compared.
{"title":"Defect and fault tolerance FPGAs by shifting the configuration data","authors":"A. Doumar, S. Kaneko, Hideo Ito","doi":"10.1109/DFTVS.1999.802905","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802905","url":null,"abstract":"The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and horse-allocation) are introduced and compared.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124259574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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