A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221186

Chung-Yu Wu, C. Chou

引用次数: 7

Abstract

A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18 um CMOS technology, the receiver chip can achieve 50.6 dB image-rejection with the power dissipation of 22.4 mW at 1.8-V voltage supply.

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用于IEEE 802.11a应用的5 ghz CMOS双正交接收器

提出了一种适用于无线局域网的5ghz CMOS双正交前端接收机。在接收机中，采用一级RLC移相器产生正交射频信号，设计有源多相滤波器抑制图像信号。它具有功耗低、芯片面积小、对寄生元件的灵敏度低等优点。该接收器芯片采用0.18 um CMOS技术，在1.8 v电压下可实现50.6 dB的图像抑制，功耗为22.4 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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