An efficient delay test generation system for combinational logic circuits

Abstract

An efficient delay test generation system for combinational logic circuits is presented. Delay testing problems are divided into gross-delay fault testing and small-delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross-delay and small-delay faults. A novel timing analysis method via functionality check is presented for delay test generation. Complete test results are demonstrated for both gross-delay and small-delay faults on several benchmark circuits.<>