An aging-aware flip-flop design based on accurate, run-time failure prediction

Abstract

As process technology continues to shrink, Negative Bias Temperature Instability (NBTI) has become a major reliability issue in CMOS circuits. NBTI degrades the threshold voltage of the PMOS transistor and, over time, causes the operating speed of the circuit to become slower (also known as the aging effect). In this paper, we introduce a new aging-aware Flip-Flop (FF) that is based on accurate, run-time Failure Prediction. In order to maintain prediction accuracy despite aging, we use two schemes: (a) the master latch in the main FF is duplicated and used as an aging monitor so that it can have the same aging effect as that of the main FF; (b) the delay element that is used for the guardband is inserted into the clock network to utilize the recovery effect of NBTI. These schemes keep the guardband virtually constant, which reduces the likelihood of both overestimating the aging effect and failing to detect it. The SPICE simulation results reveal that our FF architecture maintains its prediction accuracy for up to 10 years as a result of keeping its guardband almost completely constant.