Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231095
P. Wohl, J. Waicukauski, J. E. Colburn
Full scan designs are widely used for their indisputable benefits of predictably high test coverage, diagnosis and debug. However, for high-performance designs the cost of scan - area and delay - is not acceptable and partial scan is used instead. Unfortunately, partial scan significantly increases test generation complexity. We define a structured partial scan design methodology and specific test generation enhancements, which significantly enhance test coverage and reduce test data and cycles. Selective design areas use special types of nonscan cells which can capture a value in the last few scan load cycles. Combinational test generation is extended to work with this structured partial scan design, resulting in higher coverage and fewer patterns. Experimental results on industrial designs show consistent testability benefits.
{"title":"Enhancing testability by structured partial scan","authors":"P. Wohl, J. Waicukauski, J. E. Colburn","doi":"10.1109/VTS.2012.6231095","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231095","url":null,"abstract":"Full scan designs are widely used for their indisputable benefits of predictably high test coverage, diagnosis and debug. However, for high-performance designs the cost of scan - area and delay - is not acceptable and partial scan is used instead. Unfortunately, partial scan significantly increases test generation complexity. We define a structured partial scan design methodology and specific test generation enhancements, which significantly enhance test coverage and reduce test data and cycles. Selective design areas use special types of nonscan cells which can capture a value in the last few scan load cycles. Combinational test generation is extended to work with this structured partial scan design, resulting in higher coverage and fewer patterns. Experimental results on industrial designs show consistent testability benefits.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123409344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231101
Wei Zhao, S. Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, M. Tehranipoor
Existing commercial power sign-off tools analyze the functional mode of operation for a small time window. The detailed analysis used makes such tools impractical in determining test peak power where a large amount of scan shift cycles have to be analyzed. This paper proposes an approximate test peak power analysis flow capable of computing test peak power at each power bump in the design. The flow uses physical design information, like power grid, power bump location, packaging information, along with the design netlist. We present correlation studies, on industrial design, and show the proposed flow to correlate within 5%of the accurate commercial power sign-off tool. In addition, we demonstrate that this flow, unlike the commercial power sign-off tool, can process a very large number of transition delay tests in a reasonable time.
{"title":"A novel method for fast identification of peak current during test","authors":"Wei Zhao, S. Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, M. Tehranipoor","doi":"10.1109/VTS.2012.6231101","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231101","url":null,"abstract":"Existing commercial power sign-off tools analyze the functional mode of operation for a small time window. The detailed analysis used makes such tools impractical in determining test peak power where a large amount of scan shift cycles have to be analyzed. This paper proposes an approximate test peak power analysis flow capable of computing test peak power at each power bump in the design. The flow uses physical design information, like power grid, power bump location, packaging information, along with the design netlist. We present correlation studies, on industrial design, and show the proposed flow to correlate within 5%of the accurate commercial power sign-off tool. In addition, we demonstrate that this flow, unlike the commercial power sign-off tool, can process a very large number of transition delay tests in a reasonable time.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231097
M. Zamani, M. Tahoori, K. Chakrabarty
Reversibility as an inherent requirement of quantum computation motivates further research on reversible logic. Due to anticipated high failure rates for such technologies, thorough testing is a must for these circuits. In this paper, we present a compact test generation and application method for reversible circuits which achieves high (100%) fault coverage and can be adopted for BIST implementations. In this method, the next test pattern is the response of the reversible circuit to the previous test pattern. A test generation algorithm to minimize test time and achieve 100% fault coverage is also presented. Simulation results on a set of reversible benchmark circuits confirm that this approach can detect all single missing/repeated gate faults as well as the majority of multiple faults.
{"title":"Ping-pong test: Compact test vector generation for reversible circuits","authors":"M. Zamani, M. Tahoori, K. Chakrabarty","doi":"10.1109/VTS.2012.6231097","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231097","url":null,"abstract":"Reversibility as an inherent requirement of quantum computation motivates further research on reversible logic. Due to anticipated high failure rates for such technologies, thorough testing is a must for these circuits. In this paper, we present a compact test generation and application method for reversible circuits which achieves high (100%) fault coverage and can be adopted for BIST implementations. In this method, the next test pattern is the response of the reversible circuit to the previous test pattern. A test generation algorithm to minimize test time and achieve 100% fault coverage is also presented. Simulation results on a set of reversible benchmark circuits confirm that this approach can detect all single missing/repeated gate faults as well as the majority of multiple faults.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116550370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231068
S. Sindia, V. Agrawal
Computing with large die-size graphical processors (that need huge arrays of identical structures) in the late CMOS era is abounding with challenges due to spatial non-idealities arising from chip-to-chip and within-chip variation of MOSFET threshold voltage. In this paper, we propose a machine learning based software-framework for in-situ prediction and correction of computation corrupted due to threshold voltage variation of transistors. Based on semi-supervised training imparted to a fully connected cascade feed-forward neural network (FCCFF-NN), the NN makes an accurate prediction of the underlying hardware, creating a spatial map of faulty processing elements (PE). The faulty elements identified by the NN are avoided in future computing. Further, any transient faults occurring over and above these spatial faults are tracked, and corrected if the number of PEs involved in a particle strike is above a preset threshold. For the purposes of experimental validation, we consider a 256 × 256 array of PE. Each PE is comprised of a multiply-accumulate (MAC) block with three 8 bit registers (two for inputs and one for storing the computed result). One thousand instances of this processor array are created and PEs in each instance are randomly perturbed with threshold voltage variation. Common image processing operations such as low pass filtering and edge enhancement are performed on each of these 1000 instances. A fraction of these images (about 10%) is used to train the NN for spatial non-idealities. Based on this training, the NN is able to accurately predict the spatial extremities in 95% of all the remaining 90% of the cases. The proposed NN based error tolerance results in superior quality images whose degradation is no longer visually perceptible.
{"title":"Towards spatial fault resilience in array processors","authors":"S. Sindia, V. Agrawal","doi":"10.1109/VTS.2012.6231068","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231068","url":null,"abstract":"Computing with large die-size graphical processors (that need huge arrays of identical structures) in the late CMOS era is abounding with challenges due to spatial non-idealities arising from chip-to-chip and within-chip variation of MOSFET threshold voltage. In this paper, we propose a machine learning based software-framework for in-situ prediction and correction of computation corrupted due to threshold voltage variation of transistors. Based on semi-supervised training imparted to a fully connected cascade feed-forward neural network (FCCFF-NN), the NN makes an accurate prediction of the underlying hardware, creating a spatial map of faulty processing elements (PE). The faulty elements identified by the NN are avoided in future computing. Further, any transient faults occurring over and above these spatial faults are tracked, and corrected if the number of PEs involved in a particle strike is above a preset threshold. For the purposes of experimental validation, we consider a 256 × 256 array of PE. Each PE is comprised of a multiply-accumulate (MAC) block with three 8 bit registers (two for inputs and one for storing the computed result). One thousand instances of this processor array are created and PEs in each instance are randomly perturbed with threshold voltage variation. Common image processing operations such as low pass filtering and edge enhancement are performed on each of these 1000 instances. A fraction of these images (about 10%) is used to train the NN for spatial non-idealities. Based on this training, the NN is able to accurately predict the spatial extremities in 95% of all the remaining 90% of the cases. The proposed NN based error tolerance results in superior quality images whose degradation is no longer visually perceptible.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128495503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231090
Xi Qian, Chao Han, A. Singh
In this paper, we focus on the detection of small gate-oxide defects, which can escape production tests but lead to early-life-failures (ELF) during normal operation. Very-Low-Voltage (VLV) and MinVDD testing have been proposed in the past to screen such “weak” ICs. However, small defects that are not severe enough to trigger logic failures can still escape such tests given the fact that power supply voltage cannot be arbitrarily lowered in a given technology. We suggest a novel approach for increasing the sensitivity of detection of these small gate-oxide defects by applying timing tests in a reduced power supply environment. While not severe enough to cause logic failures, small oxide defects can still introduce observable anomalies in the timing of affected paths, which is amplified at reduced power supply voltages. Experimental simulation results using NanGate 45nm technology are provided to substantiate our conclusions.
{"title":"Detection of gate-oxide defects with timing tests at reduced power supply","authors":"Xi Qian, Chao Han, A. Singh","doi":"10.1109/VTS.2012.6231090","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231090","url":null,"abstract":"In this paper, we focus on the detection of small gate-oxide defects, which can escape production tests but lead to early-life-failures (ELF) during normal operation. Very-Low-Voltage (VLV) and MinVDD testing have been proposed in the past to screen such “weak” ICs. However, small defects that are not severe enough to trigger logic failures can still escape such tests given the fact that power supply voltage cannot be arbitrarily lowered in a given technology. We suggest a novel approach for increasing the sensitivity of detection of these small gate-oxide defects by applying timing tests in a reduced power supply environment. While not severe enough to cause logic failures, small oxide defects can still introduce observable anomalies in the timing of affected paths, which is amplified at reduced power supply voltages. Experimental simulation results using NanGate 45nm technology are provided to substantiate our conclusions.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231077
A. Trivedi, S. Mukhopadhyay
A test circuit is presented for post-silicon and on-line characterization of the energy-inflection activity of power-gated circuits (the activity when overhead energy is equal to leakage savings) under static (process) and dynamic (voltage/temperature/input) variations. The test circuit is applied to design self-adaptive power-gating for energy-efficient SRAM.
{"title":"Self-adaptive power gating with test circuit for on-line characterization of energy inflection activity","authors":"A. Trivedi, S. Mukhopadhyay","doi":"10.1109/VTS.2012.6231077","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231077","url":null,"abstract":"A test circuit is presented for post-silicon and on-line characterization of the energy-inflection activity of power-gated circuits (the activity when overhead energy is equal to leakage savings) under static (process) and dynamic (voltage/temperature/input) variations. The test circuit is applied to design self-adaptive power-gating for energy-efficient SRAM.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124642599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231069
Junyoung Park, J. Abraham
As process technology continues to shrink, Negative Bias Temperature Instability (NBTI) has become a major reliability issue in CMOS circuits. NBTI degrades the threshold voltage of the PMOS transistor and, over time, causes the operating speed of the circuit to become slower (also known as the aging effect). In this paper, we introduce a new aging-aware Flip-Flop (FF) that is based on accurate, run-time Failure Prediction. In order to maintain prediction accuracy despite aging, we use two schemes: (a) the master latch in the main FF is duplicated and used as an aging monitor so that it can have the same aging effect as that of the main FF; (b) the delay element that is used for the guardband is inserted into the clock network to utilize the recovery effect of NBTI. These schemes keep the guardband virtually constant, which reduces the likelihood of both overestimating the aging effect and failing to detect it. The SPICE simulation results reveal that our FF architecture maintains its prediction accuracy for up to 10 years as a result of keeping its guardband almost completely constant.
{"title":"An aging-aware flip-flop design based on accurate, run-time failure prediction","authors":"Junyoung Park, J. Abraham","doi":"10.1109/VTS.2012.6231069","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231069","url":null,"abstract":"As process technology continues to shrink, Negative Bias Temperature Instability (NBTI) has become a major reliability issue in CMOS circuits. NBTI degrades the threshold voltage of the PMOS transistor and, over time, causes the operating speed of the circuit to become slower (also known as the aging effect). In this paper, we introduce a new aging-aware Flip-Flop (FF) that is based on accurate, run-time Failure Prediction. In order to maintain prediction accuracy despite aging, we use two schemes: (a) the master latch in the main FF is duplicated and used as an aging monitor so that it can have the same aging effect as that of the main FF; (b) the delay element that is used for the guardband is inserted into the clock network to utilize the recovery effect of NBTI. These schemes keep the guardband virtually constant, which reduces the likelihood of both overestimating the aging effect and failing to detect it. The SPICE simulation results reveal that our FF architecture maintains its prediction accuracy for up to 10 years as a result of keeping its guardband almost completely constant.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115888487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231065
Shreepad Panth, S. Lim
In order to ensure the correctness of 3D ICs, they need to be tested both before and after their individual dies are bonded. All previous works in the area of 3D IC testing consider only stuck-at fault testing. However, 3D ICs also need to be tested for delay defects. In this work, we present a transition delay test infrastructure that can be used to test a 3D IC both before and after bonding. Furthermore, we present a methodology to test the through silicon vias (TSVs) after bonding, without necessitating regeneration of test patterns. Results show that the overhead involved is negligible. In addition, at-speed testing of circuits can suffer from large IR drop problems. In this paper, we also study the IR drop of 3D ICs during transition delay fault testing. We study how different configurations of probe pads affect the pre-bond IR drop. We also study how this IR drop changes from the pre-bond to the post-bond case.
{"title":"Transition delay fault testing of 3D ICs with IR-drop study","authors":"Shreepad Panth, S. Lim","doi":"10.1109/VTS.2012.6231065","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231065","url":null,"abstract":"In order to ensure the correctness of 3D ICs, they need to be tested both before and after their individual dies are bonded. All previous works in the area of 3D IC testing consider only stuck-at fault testing. However, 3D ICs also need to be tested for delay defects. In this work, we present a transition delay test infrastructure that can be used to test a 3D IC both before and after bonding. Furthermore, we present a methodology to test the through silicon vias (TSVs) after bonding, without necessitating regeneration of test patterns. Results show that the overhead involved is negligible. In addition, at-speed testing of circuits can suffer from large IR drop problems. In this paper, we also study the IR drop of 3D ICs during transition delay fault testing. We study how different configurations of probe pads affect the pre-bond IR drop. We also study how this IR drop changes from the pre-bond to the post-bond case.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131181625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231076
Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, D. Kwai
Capacitor mismatch is the linearity limiter of charge redistribution SAR ADCs. This paper aims at detecting and removing the mismatch induced missing-decision levels (MDLs), i.e., large positive DNLs; these errors lead to information loss that cannot be recovered by external calibration. A switched-capacitor based approach is proposed to avoid DC currents and reduce design overhead; the hardware modification also supports comparator offset compensation to improve calibration quality. Simulation results show that the proposed technique effectively improves the SAR ADC linearity in the presence of capacitor mismatch and comparator offset.
{"title":"A SAR ADC missing-decision level detection and removal technique","authors":"Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, D. Kwai","doi":"10.1109/VTS.2012.6231076","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231076","url":null,"abstract":"Capacitor mismatch is the linearity limiter of charge redistribution SAR ADCs. This paper aims at detecting and removing the mismatch induced missing-decision levels (MDLs), i.e., large positive DNLs; these errors lead to information loss that cannot be recovered by external calibration. A switched-capacitor based approach is proposed to avoid DC currents and reduce design overhead; the hardware modification also supports comparator offset compensation to improve calibration quality. Simulation results show that the proposed technique effectively improves the SAR ADC linearity in the presence of capacitor mismatch and comparator offset.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133355279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231062
Yier Jin, Y. Makris
We discuss a new approach for protecting the secrecy of internal information in an Integrated Circuit (IC) from malicious hardware Trojan threats and, thereby, enhancing hardware trust. The proposed approach is based on Register Transfer Level (RTL) code certification within a formal logic environment. The key novelty lies in the introduction of a new semantic model for the Verilog Hardware Description Language (HDL) in the Coq theorem-proving platform, which facilitates tracking and proving secrecy labels of internal sensitive data and, by extension, security properties of the design. Additional framework enhancements include the ability to encapsulate sub-module properties in the top module proof environment, thereby strengthening the ability of Coq representation to reason on hierarchically organized RTL code. We demonstrate the proposed framework on a DES encryption core, wherein we employ it to prevent secret information (e.g. round keys) leaking by hardware Trojans inserted at the RTL description of the circuit.
{"title":"Proof carrying-based information flow tracking for data secrecy protection and hardware trust","authors":"Yier Jin, Y. Makris","doi":"10.1109/VTS.2012.6231062","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231062","url":null,"abstract":"We discuss a new approach for protecting the secrecy of internal information in an Integrated Circuit (IC) from malicious hardware Trojan threats and, thereby, enhancing hardware trust. The proposed approach is based on Register Transfer Level (RTL) code certification within a formal logic environment. The key novelty lies in the introduction of a new semantic model for the Verilog Hardware Description Language (HDL) in the Coq theorem-proving platform, which facilitates tracking and proving secrecy labels of internal sensitive data and, by extension, security properties of the design. Additional framework enhancements include the ability to encapsulate sub-module properties in the top module proof environment, thereby strengthening the ability of Coq representation to reason on hierarchically organized RTL code. We demonstrate the proposed framework on a DES encryption core, wherein we employ it to prevent secret information (e.g. round keys) leaking by hardware Trojans inserted at the RTL description of the circuit.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133131043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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