{"title":"Path Breaker: a tool for the optimal design of speed independent asynchronous controllers","authors":"Yogesh Mishra, S. Sherlekar, G. Venkatesh","doi":"10.1109/EURDAC.1992.246273","DOIUrl":null,"url":null,"abstract":"The authors present a methodology for synthesizing speed independent asynchronous circuits from high-level continuous sampling plan (CSP)-like specifications. Instead of employing syntax-directed translation followed by local optimizing transformations on the resulting netlist, this method uses global dataflow analysis to directly produce an optimal controller. The method is shown to produce substantially smaller circuits than S.M. Burns's and A.J. Martin's (1988) method.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"364 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The authors present a methodology for synthesizing speed independent asynchronous circuits from high-level continuous sampling plan (CSP)-like specifications. Instead of employing syntax-directed translation followed by local optimizing transformations on the resulting netlist, this method uses global dataflow analysis to directly produce an optimal controller. The method is shown to produce substantially smaller circuits than S.M. Burns's and A.J. Martin's (1988) method.<>