A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs

Ganesh Gore, Xifan Tang, P. Gaillardon
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引用次数: 5

Abstract

Physical design for Field Programmable Gate Array (FPGA) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the FPGA design. The growing number of FPGA applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT FPGA layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern FPGA fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT FPGA fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs FPGA device.
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一种可扩展且稳健的分层布局,可实现100k-LUT fpga的24小时原型设计
现场可编程门阵列(FPGA)的物理设计是具有挑战性和耗时的,主要是由于使用完全定制的方法来积极优化FPGA设计的性能,功率和面积(P.P.A.)。越来越多的FPGA应用要求新颖的架构和更短的开发周期。自动化工具链的使用对于减少端到端的开发时间至关重要。本文提出了可扩展和自适应分层布局策略,以显着减少物理设计运行时间,并使用标准的ASIC工具链实现数百万lut的FPGA布局实现。这种方法主要利用设计的规律性,并为全局和时钟网络执行必要的馈通创建,以消除全局优化的任何要求。为了验证这种方法,我们使用商用12nm技术实现了逻辑容量从40到100k lut的现代FPGA结构的全芯片布局。我们的研究结果表明,128k-LUT FPGA结构的物理实现可以在24小时内实现,这是以前任何工作都没有证明的。与以前的工作相比,实现2.5k LUTs FPGA器件的运行时间减少了8倍。
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