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Proceedings of the 2021 International Symposium on Physical Design最新文献

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Reinforcement Learning for Placement Optimization 用于布局优化的强化学习
Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446883
Anna Goldie, Azalia Mirhoseini
In the past decade, computer systems and chips have played a key role in the success of artificial intelligence (AI). Our vision in Google Brain's Machine Learning for Systems team is to use AI to transform the way in which computer systems and chips are designed. Many core problems in systems and hardware design are combinatorial optimization or decision making tasks with state and action spaces that are orders of magnitude larger than that of standard AI benchmarks in robotics and games. In this talk, we will describe some of our latest learning based approaches to tackling such large-scale optimization problems. We will discuss our work on a new domain-transferable reinforcement learning (RL) method for optimizing chip placement [1], a long pole in hardware design. Our approach is capable of learning from past experience and improving over time, resulting in more optimized placements on unseen chip blocks as the RL agent is exposed to a larger volume of data. Our objective is to minimize power, performance, and area. We show that, in under six hours, our method can generate placements that are superhuman or comparable on modern accelerator chips, whereas existing baselines require human experts in the loop and can take several weeks.
在过去的十年中,计算机系统和芯片在人工智能(AI)的成功中发挥了关键作用。在Google Brain的机器学习系统团队中,我们的愿景是使用人工智能来改变计算机系统和芯片的设计方式。系统和硬件设计中的许多核心问题是组合优化或具有状态和行动空间的决策任务,这些任务比机器人和游戏中的标准AI基准要大几个数量级。在这次演讲中,我们将介绍一些最新的基于学习的方法来解决这种大规模的优化问题。我们将讨论我们在优化芯片放置的新领域可转移强化学习(RL)方法上的工作[1],这是硬件设计中的一个重要方面。我们的方法能够从过去的经验中学习并随着时间的推移而改进,当RL代理暴露于更大的数据量时,可以在未见过的芯片块上进行更优化的放置。我们的目标是最小化功率、性能和面积。我们证明,在不到6小时的时间里,我们的方法可以在现代加速器芯片上生成超人或可比的位置,而现有的基线需要人类专家参与,可能需要几周的时间。
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引用次数: 2
Learning Point Clouds in EDA EDA中的学习点云
Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446895
Wei Li, Guojin Chen, Haoyu Yang, Ran Chen, Bei Yu
The exploding of deep learning techniques have motivated the development in various fields, including intelligent EDA algorithms from physical implementation to design for manufacturability. Point cloud, defined as the set of data points in space, is one of the most important data representations in deep learning since it directly pre- serves the original geometric information without any discretization. However, there are still some challenges that stifle the applications of point clouds in the EDA field. In this paper, we first review previous works about deep learning in EDA and point clouds in other fields. Then, we discuss some challenges of point clouds in EDA raised by some intrinsic characteristics of point clouds. Finally, to stimulate future research, we present several possible applications of point clouds in EDA and demonstrate the feasibility by two case studies.
深度学习技术的爆炸式发展推动了各个领域的发展,包括从物理实现到可制造性设计的智能EDA算法。点云是空间中数据点的集合,是深度学习中最重要的数据表示形式之一,因为它直接保留了原始的几何信息而不进行任何离散化。然而,点云在EDA领域的应用仍然面临着一些挑战。在本文中,我们首先回顾了深度学习在EDA和其他领域的研究成果。然后,我们讨论了点云的一些固有特性给EDA中的点云带来的挑战。最后,为了促进未来的研究,我们提出了点云在EDA中的几种可能的应用,并通过两个案例证明了其可行性。
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引用次数: 2
Session details: Session 8: Monolithic 3D and Packaging Session 会议细节:会议8:单片3D和包装会议
Pub Date : 2021-03-22 DOI: 10.1145/3457132
B. Swartz
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引用次数: 0
Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes 在高级工艺节点上实现机器学习的高频低功耗数字设计
Pub Date : 2021-03-22 DOI: 10.1145/3439706.3447043
S. Nath, Vishal Khandelwal
Relentless pursuit of high-frequency low-power designs at advanced nodes necessitate achieving signoff-quality timing and power during digital implementation to minimize any over-design. With growing design sizes (1--10M instances), full flow runtime is an equally important metric and commercial implementation tools use graph-based timing analysis (GBA) to gain runtime over path-based timing analysis (PBA), at the cost of pessimism in timing. Last mile timing and power closure is then achieved through expensive PBA-driven engineering change order (ECO) loops in signoff stage. In this work, we explore "on-the-fly'' machine learning (ML) models to predict PBA timing based on GBA features, to drive digital implementation flow. Our ML model reduces the GBA vs. PBA pessimism with minimal runtime overhead, resulting in improved area/power without compromising on signoff timing closure. Experimental results obtained by integrating our technique in a commercial digital implementation tool show improvement of up to 0.92% in area, 11.7% and 1.16% in power in leakage- and total power-centric designs, respectively. Our method has a runtime overhead of $sim$3% across a suite of 5--16nm industrial designs.
在高级节点上不断追求高频低功耗设计,需要在数字实现期间实现信号质量定时和功率,以尽量减少任何过度设计。随着设计规模的增长(1- 10M实例),全流程运行时是一个同样重要的指标,商业实现工具使用基于图的时间分析(GBA)来获得运行时,而不是基于路径的时间分析(PBA),这是以时间的悲观为代价的。最后一英里计时和功率关闭,然后通过昂贵的pba驱动的工程变更命令(ECO)回路在签字阶段实现。在这项工作中,我们探索了“即时”机器学习(ML)模型来预测基于GBA特征的PBA时间,以推动数字化实施流程。我们的ML模型以最小的运行时开销减少了GBA和PBA的悲观情绪,从而在不影响签字时间关闭的情况下提高了面积/功率。通过将我们的技术集成到商业数字实现工具中获得的实验结果表明,在泄漏和总功率为中心的设计中,面积提高了0.92%,功率提高了11.7%和1.16%。我们的方法在5- 16nm工业设计套件中的运行时开销为$ $ $3%。
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引用次数: 5
Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies 新兴异构3D集成技术的物理设计挑战和解决方案
Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446903
Lingjun Zhu, S. Lim
The emerging heterogeneous 3D integration technologies provide a promising solution to improve the performance of electronic systems in the post-Moore era, but the lack of design automation solutions and the challenges in physical design are hindering the applications of these technologies. In this paper, we discuss multiple types and levels of heterogeneous integration enabled by the high-density 3D technologies. We investigate each physical implementation stage from technology setup to placement and routing, identify the design challenges proposed by heterogeneous 3D integration. This paper provides a comprehensive survey on the state-of-the-art physical design methodologies to address these challenges.
新兴的异构3D集成技术为提高后摩尔时代电子系统的性能提供了一个有前途的解决方案,但缺乏设计自动化解决方案和物理设计方面的挑战阻碍了这些技术的应用。在本文中,我们讨论了由高密度三维技术实现的多种类型和层次的异构集成。我们研究了从技术设置到放置和路由的每个物理实现阶段,确定了异构3D集成提出的设计挑战。本文对解决这些挑战的最先进的物理设计方法进行了全面的调查。
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引用次数: 0
Session details: Session 1: Opening Session and First Keynote 会议详情:第一部分:开幕式和第一主题演讲
Pub Date : 2021-03-22 DOI: 10.1145/3457126
J. Lienig
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引用次数: 0
Session details: Session 2: Machine Learning for Physical Design (1/2) 会议详情:第二部分:物理设计中的机器学习(1/2)
Pub Date : 2021-03-22 DOI: 10.1145/3457127
Jiang Hu
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引用次数: 0
Session details: Session 9: Brains, Computers and EDA 会议详情:第9部分:大脑、计算机和EDA
Pub Date : 2021-03-22 DOI: 10.1145/3457133
P. Groeneveld
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引用次数: 0
Physical Design for 3D Chiplets and System Integration 三维小芯片的物理设计与系统集成
Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446881
Frank J. C. Lee
Heterogeneous three-dimensional (3-D) package-level integration plays an increasingly important role in the design of higher functional density and lower power processors for general computing, machine learning and mobile applications. In TSMC's 3DFabricTM platform, the back end packaging technology Chip-on-Wafer-on-Substrate (CoWoS®) with the integration of High-Bandwidth Memory (HBM) has been successfully deployed in high performance compute and machine learning applications to achieve high compute throughput, while Integrated Fan-Out (InFO) packaging technology is widely used in mobile applications thanks to its small footprint. System on Integrated Chips (SoIC⃨), leveraging advanced front end Silicon process technology, offers an unprecedented bonding density for vertical stacking. Combining SoIC with CoWoS and InFO, the 3DFabric family of technologies provides a versatile and flexible platform for system design innovations. A 3DFabric design starts with system partitioning to decompose it into different functional components. In contrast to a monolithic design approach, these functional components can potentially be implemented in different technologies to optimize system performance, power, area, and cost. Then these component chips are re-integrated with 3DFabric advanced packaging technologies to form the system. There are new design challenges and opportunities arising from 3DFabric. To unleash its full potential and accelerate the product development, physical design solutions are developed. In this presentation, we will first review these advanced packaging technologies trends and design challenges. Then, we will present design solutions for 3-D chiplets and system integration.
异构三维(3-D)封装级集成在通用计算、机器学习和移动应用的高功能密度和低功耗处理器设计中发挥着越来越重要的作用。在台积电的3DFabricTM平台上,集成高带宽内存(HBM)的后端封装技术Chip-on-Wafer-on-Substrate (coos®)已成功部署在高性能计算和机器学习应用中,以实现高计算吞吐量,而集成扇出(InFO)封装技术因其占地面积小而广泛应用于移动应用。系统集成芯片(SoIC⃨),利用先进的前端硅工艺技术,为垂直堆叠提供前所未有的键合密度。将SoIC与coos和InFO相结合,3DFabric系列技术为系统设计创新提供了一个多功能和灵活的平台。3DFabric设计从系统分区开始,将其分解为不同的功能组件。与单片设计方法相比,这些功能组件可以在不同的技术中实现,以优化系统性能、功耗、面积和成本。然后将这些组件芯片与3DFabric先进的封装技术重新集成,形成系统。3d面料带来了新的设计挑战和机遇。为了释放其全部潜力并加速产品开发,开发了物理设计解决方案。在本次演讲中,我们将首先回顾这些先进封装技术的发展趋势和设计挑战。然后,我们将提出三维小芯片和系统集成的设计方案。
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引用次数: 0
Session details: Session 3: Advances in Placement 会议详情:会议3:就业进展
Pub Date : 2021-03-22 DOI: 10.1145/3457128
J. Shinnerl
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引用次数: 0
期刊
Proceedings of the 2021 International Symposium on Physical Design
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