High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI:10.1109/ATS.2007.58

S. Chun, YongJoon Kim, Sungho Kang

引用次数: 3

Abstract

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE- based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

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高mdsi:用于互连的高水平信号完整性故障测试模式生成方法

不可接受的信号完整性损失可能会对soc的功能和性能造成永久性或间歇性的损害。本文在考虑互连拓扑信息的基础上，提出了互连信号完整性问题的抽象模型和一种新的测试模式生成方法。此外，以往基于SPICE的模式生成方法过于复杂且耗时，无法生成信号完整性故障的测试模式。为了克服这一问题，我们还开发了一种新的基于抽象信号完整性故障模型的高级测试模式生成方法。实验结果表明，所提出的信号完整性故障模型对于长互连比以往的方法更精确。此外，该方法比基于spice的模式生成方法快得多。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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16th Asian Test Symposium (ATS 2007)

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