Design and analysis of Phase Locked Loop for low power wireless applications

Abstract

Phase locked loops ( PLLs) with short locking time while still providing highest stability is required in today's wireless communication system. At high frequencies, the PLL locking time is affected by the large input capacitance of the Voltage Controlled Oscillator (VCO). In this paper, we propose a fast locking PLL operating at 2.4 GHz using a low mismatch gain boosted charge pump to reduce the current mismatches and switching errors. A 4-stage inverter buffer added to the charge pump increases the driving ability of the charge pump and reduces the locking time. Using the proposed charge pump, the PLL is implemented in 90nm CMOS technology. With a reference of 24 MHz, a locking time of 413.2ns is achieved. A locking time reduction of 65.5 percentage is obtained compared to the conventional charge pump. The PLL consumes a power of 265.4 microwatts with 1V DC.