A Quaternary Decision Diagram Machine and the Optimization of its Code

2009 39th International Symposium on Multiple-Valued Logic Pub Date : 2009-05-21 DOI:10.1109/ISMVL.2009.35

Tsutomu Sasao, Hiroki Nakahara, M. Matsuura, Yoshifumi Kawamura, J. T. Butler

引用次数: 9

Abstract

We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.

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一种四元决策图机及其代码的优化

我们展示了四分决策图(qdd)在表示和评估逻辑函数方面的优势。也就是说，我们展示了如何使用QDD来实现QDD机器，从而产生高速实现。我们将QDD机器与二进制决策图(binary decision diagram, BDD)机器进行了比较，发现当选择QDD机器时，速度提高了1.28-2.02倍。我们考虑了1地址和2地址的BDD机器，以及3地址和4地址的QDD机器，并展示了一种最小化指令数量的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2009 39th International Symposium on Multiple-Valued Logic

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