The signal attenuation in chip-to-chip and backplane communication increases with the data rate. Depending on the channel’s frequency response, this attenuation may be mitigated if multi-level signaling is employed instead of binary signaling. This paper reviews the basics of binary signaling and how multi-level signaling could help improve the signal quality.
{"title":"Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial)","authors":"A. Sheikholeslami","doi":"10.1109/ISMVL.2009.64","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.64","url":null,"abstract":"The signal attenuation in chip-to-chip and backplane communication increases with the data rate. Depending on the channel’s frequency response, this attenuation may be mitigated if multi-level signaling is employed instead of binary signaling. This paper reviews the basics of binary signaling and how multi-level signaling could help improve the signal quality.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123744902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A parametron-like ternary logic element utilizing 3rd subharmonic oscillation and 3-cycle excitation is considered. By representing the oscillation phase as a vector or phasor, the basic logical operation can be described as a majority operation for vector sum of input signals. Contrary to a delay operation of phase pi (NOT operation) in parametron, two delay operations of phase 2pi /3 and 4pi /3 need to be considered. After showing the logic design of circuits using the elements, such as multiplexsors, flip-flops, counters, etc., the structure of multiway switch based on ternary Hadamard matrix is presented and the performance of multiway switches based on ternary error-correcting codes is analyzed.
{"title":"Ternary Logic by 3rd Subharmonics and its Application to Multiway Switches","authors":"T. Soma, T. Soma","doi":"10.1109/ISMVL.2009.25","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.25","url":null,"abstract":"A parametron-like ternary logic element utilizing 3rd subharmonic oscillation and 3-cycle excitation is considered. By representing the oscillation phase as a vector or phasor, the basic logical operation can be described as a majority operation for vector sum of input signals. Contrary to a delay operation of phase pi (NOT operation) in parametron, two delay operations of phase 2pi /3 and 4pi /3 need to be considered. After showing the logic design of circuits using the elements, such as multiplexsors, flip-flops, counters, etc., the structure of multiway switch based on ternary Hadamard matrix is presented and the performance of multiway switches based on ternary error-correcting codes is analyzed.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122316968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Let 2 = {0,1}. We show that the interval of partial clones containing the set of all selfdual monotonic partial functions is infinite on 2. We also study some partial clones in that interval.
{"title":"Partial Clones Containing All Selfdual Monotonic Boolean Partial Functions","authors":"L. Haddad","doi":"10.1109/ISMVL.2009.69","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.69","url":null,"abstract":"Let 2 = {0,1}. We show that the interval of partial clones containing the set of all selfdual monotonic partial functions is infinite on 2. We also study some partial clones in that interval.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117315317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We investigate a positive primitive formula closure in countable structures which establishes an algebraic framework for Constraint Satisfaction Problems on a countable set. The main question under consideration is the characterization of countable structures, called positive primitive, in which, similar to a finite case, such closure coincides with the Galois closure on predicates invariant to all polymorphisms of those structures. Next we establish criteria for existential quantifier elimination in positive primitive formulas.
{"title":"Positive Primitive Structures","authors":"B. A. Romov","doi":"10.1109/ISMVL.2009.20","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.20","url":null,"abstract":"We investigate a positive primitive formula closure in countable structures which establishes an algebraic framework for Constraint Satisfaction Problems on a countable set. The main question under consideration is the characterization of countable structures, called positive primitive, in which, similar to a finite case, such closure coincides with the Galois closure on predicates invariant to all polymorphisms of those structures. Next we establish criteria for existential quantifier elimination in positive primitive formulas.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129218440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hong Ye, Syoji Kobashi, Y. Hata, K. Taniguchi, K. Asari
In this paper, we propose an approach to extract features of center of foot pressure (COP) obtained by a load distribution sensor and apply this method to develop a biometrics personal identification system. Biometrics technology, as a method of personal identification, plays an important role in our daily lives. In our experiment, we have a user stand on load distribution sensor with slipper, and acquire pressure data during a simple motion, as touching a bell nearby by one hand but without movements of feet. We propose a biometrics personal identification system with less information, time and low space. First, we calculate the site of COP from the obtained pressure data. Features for identification are extracted from the position and the movement of COP. Second, we built a k-out-of-n system and a neural network (NN) model with the feature parameter. Third, we input test data to the two systems. Finally, we give a comparison of these two methods. We employ 11 volunteers. The experimental result reveals that the proposed identification method can achieve an accuracy of 12.0% in FRR (False Rejection Rate) and 1.0% in FAR (False Acceptance Rate).
{"title":"Biometric System by Foot Pressure Change Based on Neural Network","authors":"Hong Ye, Syoji Kobashi, Y. Hata, K. Taniguchi, K. Asari","doi":"10.1109/ISMVL.2009.16","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.16","url":null,"abstract":"In this paper, we propose an approach to extract features of center of foot pressure (COP) obtained by a load distribution sensor and apply this method to develop a biometrics personal identification system. Biometrics technology, as a method of personal identification, plays an important role in our daily lives. In our experiment, we have a user stand on load distribution sensor with slipper, and acquire pressure data during a simple motion, as touching a bell nearby by one hand but without movements of feet. We propose a biometrics personal identification system with less information, time and low space. First, we calculate the site of COP from the obtained pressure data. Features for identification are extracted from the position and the movement of COP. Second, we built a k-out-of-n system and a neural network (NN) model with the feature parameter. Third, we input test data to the two systems. Finally, we give a comparison of these two methods. We employ 11 volunteers. The experimental result reveals that the proposed identification method can achieve an accuracy of 12.0% in FRR (False Rejection Rate) and 1.0% in FAR (False Acceptance Rate).","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we first recap the rationale beyond the (non)-acceptance of multi-valued logic in implementing FPGAs so far, explaining the most critical technological and tool support details. Then, we outline the critical applications of FPGAs (e.g., emulation) where the non-binary nature can be exploited by MVL implementation. Finally, we highlight the most significant opportunities that present themselves with the transition to the nano-scale system implementations.
{"title":"Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age","authors":"Z. Zilic","doi":"10.1109/ISMVL.2009.51","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.51","url":null,"abstract":"In this paper, we first recap the rationale beyond the (non)-acceptance of multi-valued logic in implementing FPGAs so far, explaining the most critical technological and tool support details. Then, we outline the critical applications of FPGAs (e.g., emulation) where the non-binary nature can be exploited by MVL implementation. Finally, we highlight the most significant opportunities that present themselves with the transition to the nano-scale system implementations.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"361 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122920741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We introduce and investigate the concept of frozen partial co-clones. Our main motivation for studying frozen partial co-clones is that they have important applications in complexity analysis of constraints. The frozen partial co-clones lie between the co-clones and partialco-clones in the sense that the partial co-clone lattice is a refinement of the frozen partial co-clone lattice, which in turn is a refinement of the co-clone lattice. We concentrate on the Boolean domain and determine large parts of the frozen partial co-clone lattice.
{"title":"Frozen Boolean Partial Co-clones","authors":"Gustav Nordh, B. Zanuttini","doi":"10.1109/ISMVL.2009.10","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.10","url":null,"abstract":"We introduce and investigate the concept of frozen partial co-clones. Our main motivation for studying frozen partial co-clones is that they have important applications in complexity analysis of constraints. The frozen partial co-clones lie between the co-clones and partialco-clones in the sense that the partial co-clone lattice is a refinement of the frozen partial co-clone lattice, which in turn is a refinement of the co-clone lattice. We concentrate on the Boolean domain and determine large parts of the frozen partial co-clone lattice.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125318878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tsutomu Sasao, Hiroki Nakahara, M. Matsuura, Yoshifumi Kawamura, J. T. Butler
We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
{"title":"A Quaternary Decision Diagram Machine and the Optimization of its Code","authors":"Tsutomu Sasao, Hiroki Nakahara, M. Matsuura, Yoshifumi Kawamura, J. T. Butler","doi":"10.1109/ISMVL.2009.35","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.35","url":null,"abstract":"We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"463 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115941632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The synthesis and simplification of digital circuits are performed in the well known two level logic switching algebra. By increasing the representation domain to B levels it is possible to design Multiple-Valued Logic (MV Logic)digital circuits. This work proposes an algebra based on a universal set of gates which carry out operators to allow synthesis and simplification of MV Logic digital circuits. This paper addresses: the generated algebra; the algebraic form of the function to be synthesized based on the canonical form of the Sum Of Extended Product terms; the duality; and circuit simplification procedures. Combinatorial and sequential circuits are synthesized to demonstrate the correctness of the algebra. The proposed algebra allows designing any MV Logic digital circuit taking advantage of the knowledge coming from the binary circuits by extending it to the MV Logic digital circuit synthesis.
{"title":"Multiple Valued Logic Algebra for the Synthesis of Digital Circuits","authors":"Milton E. R. Romero, E. M. Martins, R. Santos","doi":"10.1109/ISMVL.2009.45","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.45","url":null,"abstract":"The synthesis and simplification of digital circuits are performed in the well known two level logic switching algebra. By increasing the representation domain to B levels it is possible to design Multiple-Valued Logic (MV Logic)digital circuits. This work proposes an algebra based on a universal set of gates which carry out operators to allow synthesis and simplification of MV Logic digital circuits. This paper addresses: the generated algebra; the algebraic form of the function to be synthesized based on the canonical form of the Sum Of Extended Product terms; the duality; and circuit simplification procedures. Combinatorial and sequential circuits are synthesized to demonstrate the correctness of the algebra. The proposed algebra allows designing any MV Logic digital circuit taking advantage of the knowledge coming from the binary circuits by extending it to the MV Logic digital circuit synthesis.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":" 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120831556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
If we know the exact consequences of each action, then we can select an action with the largest value of the objective function. In practice, we often only know these values with interval uncertainty. If two intervals intersect, then some people may prefer the alternative corresponding to the first interval, and some prefer thealternative corresponding to the second interval. How can we describe the portion of people who select the first alternative? In this paper, we provide a new theoretical justification for Hurwicz optimism-pessimism approach, and we show how this approach can be used in group decision making.
{"title":"On Decision Making under Interval Uncertainty: A New Justification of Hurwicz Optimism-Pessimism Approach and its Use in Group Decision Making","authors":"V. Huynh, Y. Nakamori, Chenyi Hu, V. Kreinovich","doi":"10.1109/ISMVL.2009.65","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.65","url":null,"abstract":"If we know the exact consequences of each action, then we can select an action with the largest value of the objective function. In practice, we often only know these values with interval uncertainty. If two intervals intersect, then some people may prefer the alternative corresponding to the first interval, and some prefer thealternative corresponding to the second interval. How can we describe the portion of people who select the first alternative? In this paper, we provide a new theoretical justification for Hurwicz optimism-pessimism approach, and we show how this approach can be used in group decision making.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134224172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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