K. Lahbacha, G. Di Capua, G. Miele, A. Maffucci, T. D. Pham, D. Allal, G. Phung, U. Arz
{"title":"Signal Integrity Analysis of Coupled Thin-Film Microstrip Lines (TFMSLs)","authors":"K. Lahbacha, G. Di Capua, G. Miele, A. Maffucci, T. D. Pham, D. Allal, G. Phung, U. Arz","doi":"10.1109/SPI57109.2023.10145525","DOIUrl":null,"url":null,"abstract":"This paper analyzes the Signal Integrity (SI) performance of thin-film microstrip lines (TFMSL), in view of their use in future communication systems, operating at unprecedented high I/O data rates (over 30 Gb/s) and high frequency (over 60-GHz). Here, various chip-level structures with coupled TFMSL are analyzed, with a special focus on mismatching and coupling associated with different choices of geometry. A frequency domain analysis is carried out using two commercial simulation tools to estimate insertion loss, crosstalk, and mode conversion. A high-speed digital link is then simulated in the time domain to evaluate the SI performance in terms of eye-diagram metrics, over a wide range of data-rate values, from 1 to 100 Gbit/s. The effect of the geometry and coupling is analyzed, and design maps are obtained, suggesting trade-off optimized choices of data-rate values, given the line geometries.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPI57109.2023.10145525","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper analyzes the Signal Integrity (SI) performance of thin-film microstrip lines (TFMSL), in view of their use in future communication systems, operating at unprecedented high I/O data rates (over 30 Gb/s) and high frequency (over 60-GHz). Here, various chip-level structures with coupled TFMSL are analyzed, with a special focus on mismatching and coupling associated with different choices of geometry. A frequency domain analysis is carried out using two commercial simulation tools to estimate insertion loss, crosstalk, and mode conversion. A high-speed digital link is then simulated in the time domain to evaluate the SI performance in terms of eye-diagram metrics, over a wide range of data-rate values, from 1 to 100 Gbit/s. The effect of the geometry and coupling is analyzed, and design maps are obtained, suggesting trade-off optimized choices of data-rate values, given the line geometries.