Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145571
Lennart P. P. B. Bohl, Katharina Scharff, X. Duan, D. Kaller, C. Schuster
In this work, the Bayesian optimization algorithm is utilized to find optimal coefficients for a first-order Continuous-Time Linear Equalizer (CTLE). The goal function for the optimization is derived from the single-bit response in the time domain. The performance of the optimized CTLE is compared to a frequency domain-based method for predicting the CTLE coefficients and a grid search over all possible combinations. The analysis is presented for two different PCB-based high-speed channels and with a 32 Gbps data rate. As a novel contribution, far-end crosstalk is included in the optimization. The resulting noisy behavior of the single-bit response is learned during the optimization as part of the Gaussian process model.
{"title":"Bayesian Optimization of First-Order Continuous-Time Linear Equalization in High-Speed Links Including Crosstalk","authors":"Lennart P. P. B. Bohl, Katharina Scharff, X. Duan, D. Kaller, C. Schuster","doi":"10.1109/SPI57109.2023.10145571","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145571","url":null,"abstract":"In this work, the Bayesian optimization algorithm is utilized to find optimal coefficients for a first-order Continuous-Time Linear Equalizer (CTLE). The goal function for the optimization is derived from the single-bit response in the time domain. The performance of the optimized CTLE is compared to a frequency domain-based method for predicting the CTLE coefficients and a grid search over all possible combinations. The analysis is presented for two different PCB-based high-speed channels and with a 32 Gbps data rate. As a novel contribution, far-end crosstalk is included in the optimization. The resulting noisy behavior of the single-bit response is learned during the optimization as part of the Gaussian process model.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123339975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145525
K. Lahbacha, G. Di Capua, G. Miele, A. Maffucci, T. D. Pham, D. Allal, G. Phung, U. Arz
This paper analyzes the Signal Integrity (SI) performance of thin-film microstrip lines (TFMSL), in view of their use in future communication systems, operating at unprecedented high I/O data rates (over 30 Gb/s) and high frequency (over 60-GHz). Here, various chip-level structures with coupled TFMSL are analyzed, with a special focus on mismatching and coupling associated with different choices of geometry. A frequency domain analysis is carried out using two commercial simulation tools to estimate insertion loss, crosstalk, and mode conversion. A high-speed digital link is then simulated in the time domain to evaluate the SI performance in terms of eye-diagram metrics, over a wide range of data-rate values, from 1 to 100 Gbit/s. The effect of the geometry and coupling is analyzed, and design maps are obtained, suggesting trade-off optimized choices of data-rate values, given the line geometries.
{"title":"Signal Integrity Analysis of Coupled Thin-Film Microstrip Lines (TFMSLs)","authors":"K. Lahbacha, G. Di Capua, G. Miele, A. Maffucci, T. D. Pham, D. Allal, G. Phung, U. Arz","doi":"10.1109/SPI57109.2023.10145525","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145525","url":null,"abstract":"This paper analyzes the Signal Integrity (SI) performance of thin-film microstrip lines (TFMSL), in view of their use in future communication systems, operating at unprecedented high I/O data rates (over 30 Gb/s) and high frequency (over 60-GHz). Here, various chip-level structures with coupled TFMSL are analyzed, with a special focus on mismatching and coupling associated with different choices of geometry. A frequency domain analysis is carried out using two commercial simulation tools to estimate insertion loss, crosstalk, and mode conversion. A high-speed digital link is then simulated in the time domain to evaluate the SI performance in terms of eye-diagram metrics, over a wide range of data-rate values, from 1 to 100 Gbit/s. The effect of the geometry and coupling is analyzed, and design maps are obtained, suggesting trade-off optimized choices of data-rate values, given the line geometries.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115944868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145554
Sameer Vashishtha, Saiyid Mohammad Irshad Rizvi, Paras Garg
In this paper, we have compared the signal quality at different points on the channel during high-speed data transmission in the Analog Front End Receiver (AFE) by analyzing the quality of eye diagrams in the presence of cost-effective packaging schemes. Simulation of Analog Front End Receiver developed in 28nm FD-SOI technology is performed with actual chip package S parameters at 1.25 Gb/s. The Simulation/Silicon Measurement results show that even a severely degraded eye diagram at the package balls does not result in a higher bit error rate. But actually, the quality of the eye diagram across the on-chip terminator resistor is the main parameter in achieving the required bit error rate specification.
{"title":"Signal Integrity Analysis of High Speed Link Analog Front End Receiver for Cost Effective Packaging Schemes","authors":"Sameer Vashishtha, Saiyid Mohammad Irshad Rizvi, Paras Garg","doi":"10.1109/SPI57109.2023.10145554","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145554","url":null,"abstract":"In this paper, we have compared the signal quality at different points on the channel during high-speed data transmission in the Analog Front End Receiver (AFE) by analyzing the quality of eye diagrams in the presence of cost-effective packaging schemes. Simulation of Analog Front End Receiver developed in 28nm FD-SOI technology is performed with actual chip package S parameters at 1.25 Gb/s. The Simulation/Silicon Measurement results show that even a severely degraded eye diagram at the package balls does not result in a higher bit error rate. But actually, the quality of the eye diagram across the on-chip terminator resistor is the main parameter in achieving the required bit error rate specification.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133440850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145569
Vinod Arjun Huddar, Shinyoun Park
Package signal transit delay is an important parameter for high-speed designs like DDR5. Package delay along with PCB delay dictates the data rates of DDR5 interface running at 4.0 Gbps and beyond. From DDR3 (third generation DDR) onwards, daisy chain routing has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyond a certain number of loadings, the fly-by starts to have trouble in keeping up with high data rates. One of the limiting factors for fly-by is package delay. To address various limitations of fly-by topology, advanced fly-by topology routing was introduced. Dependency on DRAM package delay for advanced fly-by is discussed in this paper.
{"title":"Package Propagation Delay Dependency of Advanced Fly-By Routing For Next Generation DDR5","authors":"Vinod Arjun Huddar, Shinyoun Park","doi":"10.1109/SPI57109.2023.10145569","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145569","url":null,"abstract":"Package signal transit delay is an important parameter for high-speed designs like DDR5. Package delay along with PCB delay dictates the data rates of DDR5 interface running at 4.0 Gbps and beyond. From DDR3 (third generation DDR) onwards, daisy chain routing has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyond a certain number of loadings, the fly-by starts to have trouble in keeping up with high data rates. One of the limiting factors for fly-by is package delay. To address various limitations of fly-by topology, advanced fly-by topology routing was introduced. Dependency on DRAM package delay for advanced fly-by is discussed in this paper.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125989368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145562
Ahsan Javaid, Ramachandra Achar, J. N. Tripathi
In this paper, an efficient method for analysis of power supply induced jitter (PSIJ) is presented. In the proposed approach, the noise spectrum for an arbitrary noise is generated via Fourier series and the knowledge-based neural network (KBNN) is generated to accurately predict the response of PSIJ transfer function (PSIJTF) using the training data extracted from two types of models, analytical closed-form expressions as well as computationally expensive circuit simulator. Employing KBNN based transfer function model with the noise spectrum gives reasonably accurate estimation of PSIJ for multiple input noises. A case study with 32nm CMOS technology is presented to demonstrate the validity of the proposed model compared to a circuit simulator.
{"title":"Efficient Estimation of PSIJ via Jitter Transfer Function and Knowledge-based Neural Networks","authors":"Ahsan Javaid, Ramachandra Achar, J. N. Tripathi","doi":"10.1109/SPI57109.2023.10145562","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145562","url":null,"abstract":"In this paper, an efficient method for analysis of power supply induced jitter (PSIJ) is presented. In the proposed approach, the noise spectrum for an arbitrary noise is generated via Fourier series and the knowledge-based neural network (KBNN) is generated to accurately predict the response of PSIJ transfer function (PSIJTF) using the training data extracted from two types of models, analytical closed-form expressions as well as computationally expensive circuit simulator. Employing KBNN based transfer function model with the noise spectrum gives reasonably accurate estimation of PSIJ for multiple input noises. A case study with 32nm CMOS technology is presented to demonstrate the validity of the proposed model compared to a circuit simulator.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124667325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145553
Jong-Kyun Choi, Tae-Hoon Park, Jongjae Ryu, Chanyeong Jeong, Minseok Kang, S. Moon
In this work, we present a method to derive the phase jitter (PJ) of PCI Express (PCIe) Gen3 by analyzing both random jitter (RJ) and deterministic jitter (DJ) induced by power noise in a clock network. In the previous jitter analysis methods, the impact of power noise has not been considered when analyzing the jitter of PCIe Gen3 reference clock networks. We apply the proposed method to analyze and validate the main noise sources of PCIe Gen3 PJ violations observed in a system-on-chip (SoC) design implemented at Samsung's 4-nanometer process node. Through various experiments, we found that the main cause of the violation is jitter due to power noise below 50 MHz. By modifying the power management integrated circuit (PMIC) to reduce the low-frequency noise at the PMIC output, we observed a 50% reduction in jitter in the clock network.
{"title":"Advanced Phase Jitter Analysis with Power Noise Induced Jitter Flow in PCIe Gen 3","authors":"Jong-Kyun Choi, Tae-Hoon Park, Jongjae Ryu, Chanyeong Jeong, Minseok Kang, S. Moon","doi":"10.1109/SPI57109.2023.10145553","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145553","url":null,"abstract":"In this work, we present a method to derive the phase jitter (PJ) of PCI Express (PCIe) Gen3 by analyzing both random jitter (RJ) and deterministic jitter (DJ) induced by power noise in a clock network. In the previous jitter analysis methods, the impact of power noise has not been considered when analyzing the jitter of PCIe Gen3 reference clock networks. We apply the proposed method to analyze and validate the main noise sources of PCIe Gen3 PJ violations observed in a system-on-chip (SoC) design implemented at Samsung's 4-nanometer process node. Through various experiments, we found that the main cause of the violation is jitter due to power noise below 50 MHz. By modifying the power management integrated circuit (PMIC) to reduce the low-frequency noise at the PMIC output, we observed a 50% reduction in jitter in the clock network.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145522
T. Bradde, S. Grivet-Talocia
We present a theoretical framework and related algorithms for the construction of behavioral models of linear or linearized devices. Unlike competing approaches, the proposed method is robust and guarantees theoretically the uniform stability and passivity of the models in a multivariate setting, where the model behavior depends not only on time or frequency but also on a number of design/stochastic parameters. Various examples demonstrate the high accuracy and reliability of proposed framework.
{"title":"A comprehensive framework for training stable and passive multivariate behavioral models","authors":"T. Bradde, S. Grivet-Talocia","doi":"10.1109/SPI57109.2023.10145522","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145522","url":null,"abstract":"We present a theoretical framework and related algorithms for the construction of behavioral models of linear or linearized devices. Unlike competing approaches, the proposed method is robust and guarantees theoretically the uniform stability and passivity of the models in a multivariate setting, where the model behavior depends not only on time or frequency but also on a number of design/stochastic parameters. Various examples demonstrate the high accuracy and reliability of proposed framework.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145532
M. Shokri, C. Ghobadi, J. Nourinia, P. Pinho, Zhaleh Amiri, R. Barzegari, A. Siahcheshm, F. Shapour, K. Kaboutari
This study introduces a four-element MIMO antenna that is self-isolated and appropriate for use in C-band applications for satellite communication. The antenna consists of a cross-shaped slot positioned in the center of the antenna along the chords and four T-shaped slots placed on the four main sides of the patch. The design process involved using a 3.2 mm thick FR4 substrate with a relative permittivity of 4.4 and optimizing the antenna dimensions before fabrication. The slots on the patch are responsible for creating the desired impedance bandwidth and generating remarkable isolation between the ports. Therefore, the antenna structure does not require additional elements for decoupling purposes. The experimental results show that the proposed MIMO antenna exhibits a broad impedance bandwidth ranging from 6.62 to 7.12 GHz, isolation better than 15.3 dB, ECC less than 0.008, TARC less than −5 dB, and realized peak gain of 5.77 dB.
{"title":"A Compact Four Elements Self-Isolated MIMO Antenna for C-Band Applications","authors":"M. Shokri, C. Ghobadi, J. Nourinia, P. Pinho, Zhaleh Amiri, R. Barzegari, A. Siahcheshm, F. Shapour, K. Kaboutari","doi":"10.1109/SPI57109.2023.10145532","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145532","url":null,"abstract":"This study introduces a four-element MIMO antenna that is self-isolated and appropriate for use in C-band applications for satellite communication. The antenna consists of a cross-shaped slot positioned in the center of the antenna along the chords and four T-shaped slots placed on the four main sides of the patch. The design process involved using a 3.2 mm thick FR4 substrate with a relative permittivity of 4.4 and optimizing the antenna dimensions before fabrication. The slots on the patch are responsible for creating the desired impedance bandwidth and generating remarkable isolation between the ports. Therefore, the antenna structure does not require additional elements for decoupling purposes. The experimental results show that the proposed MIMO antenna exhibits a broad impedance bandwidth ranging from 6.62 to 7.12 GHz, isolation better than 15.3 dB, ECC less than 0.008, TARC less than −5 dB, and realized peak gain of 5.77 dB.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145528
V. Kukutla, Ramachandra Achar, Wai Kong Lee
Vector Fitting (VF) is widely used for system identification via rational function approximation from tabulated data of high-speed modules. Since the algorithm is iterative in nature, minimizing its computational cost and parallel efficiency on mixed CPU and GPU environments is critical in reducing the overall time needed for convergence. In this paper, a novel Tensor-core based QR decomposition method is introduced to provide significant speedups to the most computationally expensive steps in the VF process, QR factorization and the solution to a set of linear equations, exploiting the GPU platforms with Tensor Core architectures.
{"title":"TC-QR: Tensor Core-based QR Solver for Efficient GPU-based Vector Fitting","authors":"V. Kukutla, Ramachandra Achar, Wai Kong Lee","doi":"10.1109/SPI57109.2023.10145528","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145528","url":null,"abstract":"Vector Fitting (VF) is widely used for system identification via rational function approximation from tabulated data of high-speed modules. Since the algorithm is iterative in nature, minimizing its computational cost and parallel efficiency on mixed CPU and GPU environments is critical in reducing the overall time needed for convergence. In this paper, a novel Tensor-core based QR decomposition method is introduced to provide significant speedups to the most computationally expensive steps in the VF process, QR factorization and the solution to a set of linear equations, exploiting the GPU platforms with Tensor Core architectures.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127321384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145566
A. Carlucci, S. Grivet-Talocia, Scott Mongrain, Siddarth Kulasekaran, K. Radhakrishnan
This paper presents a model order reduction approach, specifically designed for the generation of compact and efficient transient simulation models of system-level power distribution networks (PDN) of multicore processor systems. The proposed approach applies a Krylov subspace projection, with a structure that is adapted to a block-coupled state-space description of individual PDN subsystems. The latter include board-package, averaged models of integrated voltage regulators switching circuitry, and individual models of all cores including regulator inductors and capacitors. Numerical results from pro-posed reduced-order models provide major speedup with respect to SPICE with negligible loss of accuracy.
{"title":"A Structured Krylov Subspace Projection Framework for Fast Power Integrity Verification","authors":"A. Carlucci, S. Grivet-Talocia, Scott Mongrain, Siddarth Kulasekaran, K. Radhakrishnan","doi":"10.1109/SPI57109.2023.10145566","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145566","url":null,"abstract":"This paper presents a model order reduction approach, specifically designed for the generation of compact and efficient transient simulation models of system-level power distribution networks (PDN) of multicore processor systems. The proposed approach applies a Krylov subspace projection, with a structure that is adapted to a block-coupled state-space description of individual PDN subsystems. The latter include board-package, averaged models of integrated voltage regulators switching circuitry, and individual models of all cores including regulator inductors and capacitors. Numerical results from pro-posed reduced-order models provide major speedup with respect to SPICE with negligible loss of accuracy.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115519114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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