6.4 A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology

Abstract

A soaring amount of data transfer has been witnessed in recent years. By 2020, 50 billion connected devices are expected, which will generate more than 2 zettabytes of data traffic annually. Given the constraints in power & space, this explosive growth puts high stress on network infrastructure, which demands low power, high BW, and area efficient transceivers. To improve BW efficiency, modern transceivers use PAM-4 instead of NRZ to double the throughput in the same BW. However, PAM-4 introduces substantial ISI, reduces peak-to-average-ratio, and imposes non-linearity constraints compared to NRZ modulation. Scaling in CMOS technology assisted the rise of DSP-based transceivers and digital equalization schemes to compensate PAM-4 non-idealities and achieve higher SNR at the receiver output [1–3].