Pub Date : 2019-03-07DOI: 10.1109/ISSCC.2019.8662341
Yimai Peng, K. Choo, Sechang Oh, Inhee Lee, Taekwang Jang, Yejoong Kim, Jongyup Lim, D. Blaauw, D. Sylvester
Piezoelectric energy harvesters (PEHs) convert mechanical energy from vibrations into electrical energy. They have become popular in energy-autonomous IoT systems. However.’ the total energy extracted by a PEH is highly sensitive to matching between the PEH impedance and the energy extraction circuit. Prior solutions include the use of a full-bridge rectifier (FBR) and a so-called synchronous electric-charge extraction (SECE) [1], and are suitable for non-periodic vibrations. However, their extraction efficiency is low since the large internal capacitance $C_{mathrm {p}}$ (usually 10’s of nF) of the PEH (Fig. 27.2.1) prevents the output voltage from reaching its maximum power point (MPP) under a typical sinusoidal and transient excitation $(V_{mathrm {M}mathrm {P}mathrm {P}}={1/2}cdot l_{mathrm {p}}R_{mathrm {p}})$. A recently proposed technique [2], [3], [4], called bias-flip, achieves a higher extraction efficiency by forcing a predetermined constant voltage at the PEH output, $V_{mathrm {p}}$, which is then flipped every half-period of the assumed sinusoidal excitation (Fig. 27.2.1, top left). To flip $V_{mathrm {p}},$ the energy in capacitor $C_{mathrm {p}}$ is extracted using either a large external inductor [2], [3] or capacitor arrays [4]. It is then restored with the opposite polarity (Fig. 27.2.1, top). However, $V_{mathrm {M}mathrm {P}mathrm {P}}$ of the PEH varies with sinusoidal current /.’ hence, the two fixed values of $V_{mathrm {p}}$ in the flip-bias technique either over-or underestimate $V_{mathrm {M}mathrm {P}mathrm {P}}$ for much of the oscillation cycle (pattern filled regions in Fig. 27.2.1, top right). In addition, none of the prior approaches compensate for $V_{mathrm {M}mathrm {P}mathrm {P}}$-waveform amplitude changes, due to input intensity variations or decaying oscillations after an impulse, further degrading efficiency.
{"title":"27.2 An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain","authors":"Yimai Peng, K. Choo, Sechang Oh, Inhee Lee, Taekwang Jang, Yejoong Kim, Jongyup Lim, D. Blaauw, D. Sylvester","doi":"10.1109/ISSCC.2019.8662341","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662341","url":null,"abstract":"Piezoelectric energy harvesters (PEHs) convert mechanical energy from vibrations into electrical energy. They have become popular in energy-autonomous IoT systems. However.’ the total energy extracted by a PEH is highly sensitive to matching between the PEH impedance and the energy extraction circuit. Prior solutions include the use of a full-bridge rectifier (FBR) and a so-called synchronous electric-charge extraction (SECE) [1], and are suitable for non-periodic vibrations. However, their extraction efficiency is low since the large internal capacitance $C_{mathrm {p}}$ (usually 10’s of nF) of the PEH (Fig. 27.2.1) prevents the output voltage from reaching its maximum power point (MPP) under a typical sinusoidal and transient excitation $(V_{mathrm {M}mathrm {P}mathrm {P}}={1/2}cdot l_{mathrm {p}}R_{mathrm {p}})$. A recently proposed technique [2], [3], [4], called bias-flip, achieves a higher extraction efficiency by forcing a predetermined constant voltage at the PEH output, $V_{mathrm {p}}$, which is then flipped every half-period of the assumed sinusoidal excitation (Fig. 27.2.1, top left). To flip $V_{mathrm {p}},$ the energy in capacitor $C_{mathrm {p}}$ is extracted using either a large external inductor [2], [3] or capacitor arrays [4]. It is then restored with the opposite polarity (Fig. 27.2.1, top). However, $V_{mathrm {M}mathrm {P}mathrm {P}}$ of the PEH varies with sinusoidal current /.’ hence, the two fixed values of $V_{mathrm {p}}$ in the flip-bias technique either over-or underestimate $V_{mathrm {M}mathrm {P}mathrm {P}}$ for much of the oscillation cycle (pattern filled regions in Fig. 27.2.1, top right). In addition, none of the prior approaches compensate for $V_{mathrm {M}mathrm {P}mathrm {P}}$-waveform amplitude changes, due to input intensity variations or decaying oscillations after an impulse, further degrading efficiency.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"11 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120922479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662329
H. Kennedy, R. Bodnar, Teerasak Lee, W. Redman-White
As well as transferring power, inductively coupled systems such as RFID and wireless charging commonly require a downlink channel to transfer data to the receiving function, for simplicity usually using the same carrier frequency used for the power transfer. A high-Q resonant transmitter coil is highly desirable to create the strong magnetic field required fora practical operating range. However, this not only raises major problems with sensitivity to tolerances and environmental factors, but also seriously restricts the available bandwidth and hence downlink data-rate. Amplitude Shift or On-Off Keying (ASK/OOK) are commonly used to allow simple demodulation, but in addition to the 0 factor restricting the data-rate, the average power transfer will be reduced by around 50%. Frequency Shift Keying (FSK) or Phase Shift Keying (PSK) are attractive inasmuch as the nominally constant envelope provides a potentially higher power throughput, but the data-rate issue with a high-Q transmitter still remains. This is obvious for FSK, where by definition operation cannot be maintained away from the transmitter antenna’s resonance frequency. Less obviously, for PSK applied to a nominally constant frequency carrier, the stored energy in the transmit tuned circuit will slow the phase transitions making demodulation more difficult; for binary PSK the amplitude will also drop significantly at each symbol transition. Note that the receiver 0 factor is usually lower to avoid the need for active tuning in a micropower circuit.
{"title":"28.4 A High-Q Resonant Inductive Link Transmit Modulator/Driver for Enhanced Power and FSK/PSK Data Transfer Using Adaptive-Predictive Phase-Continuous Switching Fractional-Capacitance Tuning","authors":"H. Kennedy, R. Bodnar, Teerasak Lee, W. Redman-White","doi":"10.1109/ISSCC.2019.8662329","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662329","url":null,"abstract":"As well as transferring power, inductively coupled systems such as RFID and wireless charging commonly require a downlink channel to transfer data to the receiving function, for simplicity usually using the same carrier frequency used for the power transfer. A high-Q resonant transmitter coil is highly desirable to create the strong magnetic field required fora practical operating range. However, this not only raises major problems with sensitivity to tolerances and environmental factors, but also seriously restricts the available bandwidth and hence downlink data-rate. Amplitude Shift or On-Off Keying (ASK/OOK) are commonly used to allow simple demodulation, but in addition to the 0 factor restricting the data-rate, the average power transfer will be reduced by around 50%. Frequency Shift Keying (FSK) or Phase Shift Keying (PSK) are attractive inasmuch as the nominally constant envelope provides a potentially higher power throughput, but the data-rate issue with a high-Q transmitter still remains. This is obvious for FSK, where by definition operation cannot be maintained away from the transmitter antenna’s resonance frequency. Less obviously, for PSK applied to a nominally constant frequency carrier, the stored energy in the transmit tuned circuit will slow the phase transitions making demodulation more difficult; for binary PSK the amplitude will also drop significantly at each symbol transition. Note that the receiver 0 factor is usually lower to avoid the need for active tuning in a micropower circuit.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130764418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A malignant tumor consists of rapidly growing cancer cells, and requires a dedicated blood supply to provide oxygen and nutrients. Therefore, vascular endothelial growth factor (VEGF), a signal protein produced by cells stimulating angiogenesis, is considered as a key biomarker in clinical diagnosis of cancers [1], [2]. There are already existing methods for the VEGF detection requiring advanced instruments and complex protocols [2]. Recently, significant progress has been achieved in biosensors for the detection and quantification of VEGF using synthetic receptors [2]. In particular, a capacitive biosensor detects the change of dielectric properties when the receptor binds to VEGF, and capacitance change can be used to quantify the reactions. However, the sensitivity of the capacitive biosensors still needs to be improved for use in cancer diagnosis.
{"title":"11.3 A Capacitive Biosensor for Cancer Diagnosis Using a Functionalized Microneedle and a 13.7b-Resolution Capacitance-to-Digital Converter from 1 to 100nF","authors":"Seungwoo Song, Jukwan Na, Moonhyung Jang, Hyeyeon Lee, Hyesoo Lee, Y. Lim, Heonjin Choi, Youngcheol Chae","doi":"10.1109/ISSCC.2019.8662522","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662522","url":null,"abstract":"A malignant tumor consists of rapidly growing cancer cells, and requires a dedicated blood supply to provide oxygen and nutrients. Therefore, vascular endothelial growth factor (VEGF), a signal protein produced by cells stimulating angiogenesis, is considered as a key biomarker in clinical diagnosis of cancers [1], [2]. There are already existing methods for the VEGF detection requiring advanced instruments and complex protocols [2]. Recently, significant progress has been achieved in biosensors for the detection and quantification of VEGF using synthetic receptors [2]. In particular, a capacitive biosensor detects the change of dielectric properties when the receptor binds to VEGF, and capacitance change can be used to quantify the reactions. However, the sensitivity of the capacitive biosensors still needs to be improved for use in cancer diagnosis.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115834787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662389
Tianyu Jia, R. Joseph, Jie Gu
Cycle-by-cycle dynamic timing slack (DTS), which represents extra timing margin from the critical-path timing slack reported by the static timing analysis (STA), has been observed at both program level and instruction level. Conventional dynamic voltage and frequency scaling (DVFS) works at the program level and does not provide adequate frequency-scaling granularity for instruction-level timing management [1]. Razor-based techniques leverage error detection to exploit the DTS on a cycle-by-cycle basis [2]. However, it requires additional error-detection circuits and architecture-level co-design for error recovery [3]. Supply droop-based adaptive clocking was used to reduce timing margin under PVT variation, but does not address the instruction-level timing variation [4]. Recently, instruction-based adaptive clock schemes have been introduced to enhance a CPU’s operation [5–6]. For example, instruction types at the execution stage were used to provide timing control for a simple pipeline structure. However, this scheme lacks adequate consideration for other pipeline stages whose timing may not be opcode dependent [5]. In [6], the instruction-execution sequence was evaluated at the compiler level with the timing encoded into the instruction code. The scheme considers all pipeline stages but relies on in-order execution of instructions for proper timing encoding from the compiler.
{"title":"19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution","authors":"Tianyu Jia, R. Joseph, Jie Gu","doi":"10.1109/ISSCC.2019.8662389","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662389","url":null,"abstract":"Cycle-by-cycle dynamic timing slack (DTS), which represents extra timing margin from the critical-path timing slack reported by the static timing analysis (STA), has been observed at both program level and instruction level. Conventional dynamic voltage and frequency scaling (DVFS) works at the program level and does not provide adequate frequency-scaling granularity for instruction-level timing management [1]. Razor-based techniques leverage error detection to exploit the DTS on a cycle-by-cycle basis [2]. However, it requires additional error-detection circuits and architecture-level co-design for error recovery [3]. Supply droop-based adaptive clocking was used to reduce timing margin under PVT variation, but does not address the instruction-level timing variation [4]. Recently, instruction-based adaptive clock schemes have been introduced to enhance a CPU’s operation [5–6]. For example, instruction types at the execution stage were used to provide timing control for a simple pipeline structure. However, this scheme lacks adequate consideration for other pipeline stages whose timing may not be opcode dependent [5]. In [6], the instruction-execution sequence was evaluated at the compiler level with the timing encoded into the instruction code. The scheme considers all pipeline stages but relies on in-order execution of instructions for proper timing encoding from the compiler.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The number of studies on closed-loop detection and electrical stimulation systems [1]–[2] for efficient control of neurological disorders is increasing, because recent clinical studies have shown their efficiency and usefulness in symptom suppression. Electrical stimulation can produce enough stimulation to affect a large range of nerves. However, all nerves near the stimulus are excited and hurt, and over time, currents start to exceed acceptable limits. Therefore, optogenetic stimulation [3]–[4] has become compelling in recent years due to several advantages: (1) no artificial noise on the EEG; (2) ability to stimulate specific nerves; and (3) no injurious effects on nerves. In this study, a wireless programmable stimulating system-on-chip (WPSSoC) is reported that provides wireless open/closed-loop optogenetic and electrical stimulation to improve treatment for epilepsy suppression. The system is demonstrated on programmable stimulation parameters wirelessly controlled by a software Graphical User Interface (GUI) on a computer. Moreover, an animal experiment conducted on optogenetic tissue was successful, thereby demonstrating that the nerve injury on optogenetic stimulation is lower than that of electrical stimulation.
{"title":"22.7 A Programmable Wireless EEG Monitoring SoC with Open/Closed-Loop Optogenetic and Electrical Stimulation for Epilepsy Control","authors":"Shuenn-Yuh Lee, Chieh Tsou, Peng-Wei Huang, Po-Hao Cheng, Chi-Chung Liao, Zhan-Xien Liao, Hao-Yun Lee, Chou-Ching K. Lin, Chia-Hsiang Hsieh","doi":"10.1109/ISSCC.2019.8662385","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662385","url":null,"abstract":"The number of studies on closed-loop detection and electrical stimulation systems [1]–[2] for efficient control of neurological disorders is increasing, because recent clinical studies have shown their efficiency and usefulness in symptom suppression. Electrical stimulation can produce enough stimulation to affect a large range of nerves. However, all nerves near the stimulus are excited and hurt, and over time, currents start to exceed acceptable limits. Therefore, optogenetic stimulation [3]–[4] has become compelling in recent years due to several advantages: (1) no artificial noise on the EEG; (2) ability to stimulate specific nerves; and (3) no injurious effects on nerves. In this study, a wireless programmable stimulating system-on-chip (WPSSoC) is reported that provides wireless open/closed-loop optogenetic and electrical stimulation to improve treatment for epilepsy suppression. The system is demonstrated on programmable stimulation parameters wirelessly controlled by a software Graphical User Interface (GUI) on a computer. Moreover, an animal experiment conducted on optogenetic tissue was successful, thereby demonstrating that the nerve injury on optogenetic stimulation is lower than that of electrical stimulation.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115248592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662321
M. Smit, K. Williams, J. Tol
The market for photonic integrated circuits (PICs) is rapidly growing. Photonic integration which is now the dominant technology in high-bandwidth and long-distance telecommunications is increasingly applied to shorter distances within data centers. Now, it is set to become also dominant in many other fields: PICs offer compelling performance advances in terms of precision, bandwidth, and energy efficiency. To enable uptake in new sectors, the availability of highly standardized (generic) photonic-integration-platform technologies is of key importance, as this separates design from technology, reducing barriers for new entrants. Another major challenge is low-cost energy-efficient integration of photonics with the electronic circuitry that is used for driving and controlling the photonic IC and processing its information. Today, the major platform technologies are indium phosphide (InP)-based monolithic integration and silicon (Si)-based photonics. InP technology offers integration of the full suite of photonic components, including lasers, optical amplifiers, and high-performance modulators. While Si photonics offers better compatibility with CMOS process facilities, it lacks the most important photonic building blocks: lasers and optical amplifiers. In this paper, we describe the current status and directions for future developments of InP-based generic integration, and we compare the potential of InP photonics and Si photonics for integration with controlling electronics. In what follows, we will focus in Section 1 on similarities and differences between InP and Si photonics. In Section 2, we will give a concise overview of the present status of this technology and how it compares with Silicon photonics. In sections 3 and 4 we will discuss membrane-based technologies which support efficient integration with electronics.
{"title":"1.3 Integration of Photonics and Electronics","authors":"M. Smit, K. Williams, J. Tol","doi":"10.1109/ISSCC.2019.8662321","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662321","url":null,"abstract":"The market for photonic integrated circuits (PICs) is rapidly growing. Photonic integration which is now the dominant technology in high-bandwidth and long-distance telecommunications is increasingly applied to shorter distances within data centers. Now, it is set to become also dominant in many other fields: PICs offer compelling performance advances in terms of precision, bandwidth, and energy efficiency. To enable uptake in new sectors, the availability of highly standardized (generic) photonic-integration-platform technologies is of key importance, as this separates design from technology, reducing barriers for new entrants. Another major challenge is low-cost energy-efficient integration of photonics with the electronic circuitry that is used for driving and controlling the photonic IC and processing its information. Today, the major platform technologies are indium phosphide (InP)-based monolithic integration and silicon (Si)-based photonics. InP technology offers integration of the full suite of photonic components, including lasers, optical amplifiers, and high-performance modulators. While Si photonics offers better compatibility with CMOS process facilities, it lacks the most important photonic building blocks: lasers and optical amplifiers. In this paper, we describe the current status and directions for future developments of InP-based generic integration, and we compare the potential of InP photonics and Si photonics for integration with controlling electronics. In what follows, we will focus in Section 1 on similarities and differences between InP and Si photonics. In Section 2, we will give a concise overview of the present status of this technology and how it compares with Silicon photonics. In sections 3 and 4 we will discuss membrane-based technologies which support efficient integration with electronics.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134032474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662458
Reza Pazhouhandeh, Gerard O’Leary, Iliya Weisspapir, David M. Groppe, Xuan-Thuan Nguyen, K. Abdelhalim, Hamed Mazhab-Jafari, T. Valiante, P. Carlen, N. Verma, R. Genov
An emerging neuromodulation approach to treat disorders such as intractable epilepsy and Alzheimer’s disease is to use electrical stimulation triggered by pathological brain states, conventionally delivered via intracranially implanted electrodes as shown in Fig. 22.8.1 (top, left). A safer, non-invasive technology for closed-loop deep-brain neuromodulation (DBN) to treat neural disorders has been a holy grail of neuroscience for decades. Recent clinical studies of non-invasive transcranial stimulation are showing increasing promise. For instance, there is evidence that stimulation in certain stages of sleep can improve memory. This work demonstrates a platform technology for enabling such studies and protocols, where brain-state-dependent stimulation enables therapy in either conventional invasive or emerging non-invasive neuromodulation modalities.
{"title":"22.8 Adaptively Clock-Boosted Auto-Ranging Responsive Neurostimulator for Emerging Neuromodulation Applications","authors":"Reza Pazhouhandeh, Gerard O’Leary, Iliya Weisspapir, David M. Groppe, Xuan-Thuan Nguyen, K. Abdelhalim, Hamed Mazhab-Jafari, T. Valiante, P. Carlen, N. Verma, R. Genov","doi":"10.1109/ISSCC.2019.8662458","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662458","url":null,"abstract":"An emerging neuromodulation approach to treat disorders such as intractable epilepsy and Alzheimer’s disease is to use electrical stimulation triggered by pathological brain states, conventionally delivered via intracranially implanted electrodes as shown in Fig. 22.8.1 (top, left). A safer, non-invasive technology for closed-loop deep-brain neuromodulation (DBN) to treat neural disorders has been a holy grail of neuroscience for decades. Recent clinical studies of non-invasive transcranial stimulation are showing increasing promise. For instance, there is evidence that stimulation in certain stages of sleep can improve memory. This work demonstrates a platform technology for enabling such studies and protocols, where brain-state-dependent stimulation enables therapy in either conventional invasive or emerging non-invasive neuromodulation modalities.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132897179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662296
T. Kuo, Yi-Wei Huang, Pai-Yi Wang
Switching buck converters with dynamic voltage scaling (DVS) for high-efficiency high-performance computing applications need to reduce the output-voltage undershoot/overshoot ($V_{mathrm {US}}$/$V_{mathrm {OS}}$) and settling time $t_{mathrm {S}}$ under a large and fast-changing load current ($I_{mathrm {load}}$). A multiphase topology with a fast load-transient response meets these requirements. The load-transient response can be accurately accelerated to reduce $V_{mathrm {US}}$/$V_{mathrm {OS}}$ and $t_{mathrm {S}}$ to near their ideal values by measuring the output-capacitor current $I_{mathrm {C}mathrm {o}}$ to control the inductor’s energizing and de-energizing times, since $I_{mathrm {C}mathrm {o}}$ instantly reflects the load-current transients. An integrated capacitor-current sensor (CCS) [1] can be used to sense $I_{mathrm {C}mathrm {o}}$ by emulating the output-capacitor impedance $Z_{mathrm {C}mathrm {o}}$: comprising capacitance $C_{mathrm{O}}$, the equivalent series resistance $R_{mathrm {E}mathrm {S}mathrm {R}}$, and inductance $L_{mathrm {E}mathrm {S}mathrm {L}}$. However, $I_{mathrm {C}mathrm {o}}$ will be inaccurately sensed if $Z_{mathrm {C}mathrm {o}}$ varies with different output voltages $V_{mathrm{O}}$, manufacturing variations, PCB parasitics, temperature, and aging. The state-of-the-art CCS calibration technique [1] for such $Z_{mathrm {C}mathrm {o}}$ variations is suitable for foreground operation and DVS with pre-characterized $V_{mathrm{O}}$ levels, since calibration starts immediately after being enabled and runs continuously until it ends. The CCS in [1] is calibrated with a low-power cost-effective comparator and successive approximation logic, with an acceptable calibration time $T_{mathrm{CAL}}$ for foreground operation. To broaden the range of applications, this work proposes an ADC-based CCS and a background CCS calibration (BCC) controller. The proposed CCS uses a flash ADC with a dynamic reference to shorten $T_{mathrm {C}mathrm {A}mathrm {L}}$. The BCC controller automatically finds a quasi-steady state (OS), namely a short period of steady-state behavior when there is no load transient or DVS event, to trigger CCS calibration, and can interrupt CCS calibration when a load transient or a DVS event occurs. Since OSs generally exist, the BCC with a short $T_{mathrm{CAL}}$ can increase the flexibility of scheduling both load transients and DVS events. Thus, it is suitable for DVS with numerous $V_{mathrm{O}}$ levels that account for in situ parameter variations.
{"title":"27.6 Background Capacitor-Current-Sensor Calibration of DC-DC Buck Converter with DVS for Accurately Accelerating Load-Transient Response","authors":"T. Kuo, Yi-Wei Huang, Pai-Yi Wang","doi":"10.1109/ISSCC.2019.8662296","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662296","url":null,"abstract":"Switching buck converters with dynamic voltage scaling (DVS) for high-efficiency high-performance computing applications need to reduce the output-voltage undershoot/overshoot ($V_{mathrm {US}}$/$V_{mathrm {OS}}$) and settling time $t_{mathrm {S}}$ under a large and fast-changing load current ($I_{mathrm {load}}$). A multiphase topology with a fast load-transient response meets these requirements. The load-transient response can be accurately accelerated to reduce $V_{mathrm {US}}$/$V_{mathrm {OS}}$ and $t_{mathrm {S}}$ to near their ideal values by measuring the output-capacitor current $I_{mathrm {C}mathrm {o}}$ to control the inductor’s energizing and de-energizing times, since $I_{mathrm {C}mathrm {o}}$ instantly reflects the load-current transients. An integrated capacitor-current sensor (CCS) [1] can be used to sense $I_{mathrm {C}mathrm {o}}$ by emulating the output-capacitor impedance $Z_{mathrm {C}mathrm {o}}$: comprising capacitance $C_{mathrm{O}}$, the equivalent series resistance $R_{mathrm {E}mathrm {S}mathrm {R}}$, and inductance $L_{mathrm {E}mathrm {S}mathrm {L}}$. However, $I_{mathrm {C}mathrm {o}}$ will be inaccurately sensed if $Z_{mathrm {C}mathrm {o}}$ varies with different output voltages $V_{mathrm{O}}$, manufacturing variations, PCB parasitics, temperature, and aging. The state-of-the-art CCS calibration technique [1] for such $Z_{mathrm {C}mathrm {o}}$ variations is suitable for foreground operation and DVS with pre-characterized $V_{mathrm{O}}$ levels, since calibration starts immediately after being enabled and runs continuously until it ends. The CCS in [1] is calibrated with a low-power cost-effective comparator and successive approximation logic, with an acceptable calibration time $T_{mathrm{CAL}}$ for foreground operation. To broaden the range of applications, this work proposes an ADC-based CCS and a background CCS calibration (BCC) controller. The proposed CCS uses a flash ADC with a dynamic reference to shorten $T_{mathrm {C}mathrm {A}mathrm {L}}$. The BCC controller automatically finds a quasi-steady state (OS), namely a short period of steady-state behavior when there is no load transient or DVS event, to trigger CCS calibration, and can interrupt CCS calibration when a load transient or a DVS event occurs. Since OSs generally exist, the BCC with a short $T_{mathrm{CAL}}$ can increase the flexibility of scheduling both load transients and DVS events. Thus, it is suitable for DVS with numerous $V_{mathrm{O}}$ levels that account for in situ parameter variations.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130809860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662455
L. Everson, S. Sapatnekar, C. Kim
Single-source shortest path (SSP) problems have a rich history of algorithm development [1–3]. SSP has many applications including AI decision making, robot navigation, VLSI signal routing, autonomous vehicles and many other classes of problems that can be mapped onto graphs. Conventional algorithms rely on sequentially traversing the search space, which is inherently limited by traditional computer architecture. In graphs which become very large, this slow processing time can become a bottleneck in real world applications. We propose a time-based ASIC to address this issue. Our design leverages a dedicated hardware implementation to solve these problems in linear time complexity with superior energy efficiency. A $40times40$ four-neighbor grid implements a wavefront (WF) expansion with a first-in lockout mechanism to enable traceback. Outside the array, a programmable resistive ladder provides bias voltages to the edge cells, which enables pulse shaping reminiscent of the A* algorithm [3].
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