{"title":"A new current-mode sense amplifier for low-voltage low-power SRAM","authors":"Jinn-Shyan Wang, Hong-Yu Lee","doi":"10.1109/ASIC.1998.722884","DOIUrl":null,"url":null,"abstract":"A new current-mode sense amplifier is proposed and it can be used in the design of a low-voltage low-power SRAM for ASIC applications. In the new current-mode sense amplifier a modified current-conveyor is used to prevent the pattern dependent problem which is overlooked in the previous designs. Simulation results show the conventional circuits will fail and the new circuit can work if V/sub DD/=1.5 V and an industrial 0.35 /spl mu/m CMOS technology is used. Power consumption of the new circuit with V/sub DD/=1.5 V is only 6%/spl sim/39% of the conventional circuits running at V/sub DD/=2.0 V. A 128/spl times/8 SRAM using the new circuit for V/sub DD/=2.0 V in a 0.6 /spl mu/m CMOS technology is also designed and successfully applied in an 8-bit low-power microcontroller.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"291 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 24
Abstract
A new current-mode sense amplifier is proposed and it can be used in the design of a low-voltage low-power SRAM for ASIC applications. In the new current-mode sense amplifier a modified current-conveyor is used to prevent the pattern dependent problem which is overlooked in the previous designs. Simulation results show the conventional circuits will fail and the new circuit can work if V/sub DD/=1.5 V and an industrial 0.35 /spl mu/m CMOS technology is used. Power consumption of the new circuit with V/sub DD/=1.5 V is only 6%/spl sim/39% of the conventional circuits running at V/sub DD/=2.0 V. A 128/spl times/8 SRAM using the new circuit for V/sub DD/=2.0 V in a 0.6 /spl mu/m CMOS technology is also designed and successfully applied in an 8-bit low-power microcontroller.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
