3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

Jonghae Kim, J. Plouchart, N. Zamdmer, M. Sherony, Liang-Hung Lu, Yue Tan, Meeyoung Yoon, K. Jenkins, Mahender Kumar, A. Ray, L. Wagner
{"title":"3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits","authors":"Jonghae Kim, J. Plouchart, N. Zamdmer, M. Sherony, Liang-Hung Lu, Yue Tan, Meeyoung Yoon, K. Jenkins, Mahender Kumar, A. Ray, L. Wagner","doi":"10.1109/VLSIC.2003.1221153","DOIUrl":null,"url":null,"abstract":"This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35

Abstract

This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于集成射频电路的SOI CMOS技术中的三维垂直平行板电容器
本文介绍了采用0.12 /spl mu/m SOI CMOS工艺制备的高q、高密度三维垂直平行板(VPP)电容器。有效电容密度为1.76 fF//spl mu/m/sup 2/。对于20pf VPP电容器,在1ghz时的质量因数为22。并首次提出了VPP电容模型,用于VPP电容的设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
RF CMOS comes of age A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology On-die droop detector for analog sensing of power supply noise A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1