{"title":"Power aware combination of transposed-form and direct-form FIR polyphase decimators for Sigma-Delta ADCs","authors":"A. Shahein, M. Becker, N. Lotze, Y. Manoli","doi":"10.1109/MWSCAS.2009.5236021","DOIUrl":null,"url":null,"abstract":"This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator for a 3rd order low-pass Sigma-Delta modulator with an oversampling ratio of 24 is used as a case study. Different topologies using both transposed and direct form structures have been implemented for power consumption investigation. The designs were synthesized in 0.13µm CMOS technology.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"115 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2009.5236021","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator for a 3rd order low-pass Sigma-Delta modulator with an oversampling ratio of 24 is used as a case study. Different topologies using both transposed and direct form structures have been implemented for power consumption investigation. The designs were synthesized in 0.13µm CMOS technology.