Power aware combination of transposed-form and direct-form FIR polyphase decimators for Sigma-Delta ADCs

A. Shahein, M. Becker, N. Lotze, Y. Manoli
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引用次数: 2

Abstract

This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator for a 3rd order low-pass Sigma-Delta modulator with an oversampling ratio of 24 is used as a case study. Different topologies using both transposed and direct form structures have been implemented for power consumption investigation. The designs were synthesized in 0.13µm CMOS technology.
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用于Sigma-Delta adc的转置形式和直接形式FIR多相抽取器的功率感知组合
本文介绍了一种新的滤波器选择准则,用于高能效FIR多相抽取器的转置滤波器和直接滤波器的选择。使用所提出的准则计算的功耗与模拟结果之间的误差小于5%。提出了一种用于高能效FIR多相抽取器的转置滤波器和直置滤波器的组合结构。用过采样比为24的三阶低通Sigma-Delta调制器的抽取器作为实例研究。使用转置和直接形式结构的不同拓扑已经实现用于功耗调查。设计采用0.13µm CMOS技术合成。
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