Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236000
N. Medrano, A. Bayo, B. Calvo, S. Celma, M. T. Sanz
The ever-increasing application of sensor networks in many different fields is causing a growing demand of low-cost passive sensors for monitoring physical variables such as temperature, pressure or ambient humidity. These sensors need a conditioning circuit that allows an easy interface to a microcontroller, taking advantage of the full range of the sensor and reducing the microcontroller requirements. This paper presents a conditioning system designed to transform the output of low-cost resistive sensors to a digital value. The system consists of a voltage to frequency converter circuit and the implementation of a frequency to code algorithm programmed on a low-power microcontroller. The conversion circuit was designed to use the full frequency range available, providing a good resolution while the resulting quasi-digital signals are compatible to the logic levels of a standard low-power microcontroller. The algorithm provides a suitable accuracy at low requirements in microcontroller resources.
{"title":"Analogue-digital interface for low-cost sensors in low-power sensing networks","authors":"N. Medrano, A. Bayo, B. Calvo, S. Celma, M. T. Sanz","doi":"10.1109/MWSCAS.2009.5236000","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236000","url":null,"abstract":"The ever-increasing application of sensor networks in many different fields is causing a growing demand of low-cost passive sensors for monitoring physical variables such as temperature, pressure or ambient humidity. These sensors need a conditioning circuit that allows an easy interface to a microcontroller, taking advantage of the full range of the sensor and reducing the microcontroller requirements. This paper presents a conditioning system designed to transform the output of low-cost resistive sensors to a digital value. The system consists of a voltage to frequency converter circuit and the implementation of a frequency to code algorithm programmed on a low-power microcontroller. The conversion circuit was designed to use the full frequency range available, providing a good resolution while the resulting quasi-digital signals are compatible to the logic levels of a standard low-power microcontroller. The algorithm provides a suitable accuracy at low requirements in microcontroller resources.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115427878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236111
V. Honkote, B. Taskin
Resonant clocking technologies are the next generation clocking technologies with GHz range frequency generation and effective power reduction features. The resonant standing wave oscillator technology (with mobius implementation) combines the advantages of resonant traveling wave oscillator and the traditional resonant standing wave oscillator. The high frequency in the mobius standing wave oscillator implementation is often susceptible to implementation parameters such as the variation in the total capacitive load distribution between the rings topology. In this paper, a novel capacitive load balancing methodology is presented for the mobius implementation of resonant standing wave oscillator. The experiments performed on the IBM R1-R5 benchmark circuits demonstrate an average improvement of 4.66X in capacitive load balancing.
{"title":"Capacitive load balancing for mobius implementation of standing wave oscillator","authors":"V. Honkote, B. Taskin","doi":"10.1109/MWSCAS.2009.5236111","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236111","url":null,"abstract":"Resonant clocking technologies are the next generation clocking technologies with GHz range frequency generation and effective power reduction features. The resonant standing wave oscillator technology (with mobius implementation) combines the advantages of resonant traveling wave oscillator and the traditional resonant standing wave oscillator. The high frequency in the mobius standing wave oscillator implementation is often susceptible to implementation parameters such as the variation in the total capacitive load distribution between the rings topology. In this paper, a novel capacitive load balancing methodology is presented for the mobius implementation of resonant standing wave oscillator. The experiments performed on the IBM R1-R5 benchmark circuits demonstrate an average improvement of 4.66X in capacitive load balancing.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116668714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235955
P. G. López, Raul J. Sandoval Gomez, Fernando Vazquez Torres
The schedulers for Concurrent Real-time Tasks are algorithms that are allocate in processor resources to the different tasks and at different times, in this sense, it is necessary to measure their efficiency based on the time constraints of the tasks in real time, this measurement should be performed on local and global. This paper proposes the measurement of this efficiency through the operating times and delay times of tasks and their instances.
{"title":"Measuring the efficiency of schedulers for Concurrent Real-time Tasks in uniprocessor systems","authors":"P. G. López, Raul J. Sandoval Gomez, Fernando Vazquez Torres","doi":"10.1109/MWSCAS.2009.5235955","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235955","url":null,"abstract":"The schedulers for Concurrent Real-time Tasks are algorithms that are allocate in processor resources to the different tasks and at different times, in this sense, it is necessary to measure their efficiency based on the time constraints of the tasks in real time, this measurement should be performed on local and global. This paper proposes the measurement of this efficiency through the operating times and delay times of tasks and their instances.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122365651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236131
R. Vázquez-Medina, A. Díaz-Méndez, M. Cruz‐Irisson, J. L. Del-Río-Correa, J. López-Hernández
In this paper, the Birkhoff's Ergodic Theorem, mixing property of the one-dimensional maps, strong convergence criterion and Kullbak-Leibler divergence are applied in order to design chaotic analogical noise generators using MOS QT Circuits, which are governed by one-dimensional chaotic maps. In this work an analogical circuit is used, which have a structure of transistors MOS that operates in current-mode and that uses the transconductance linear principle.
{"title":"Statistical criteria of design for chaotic analog noise generators","authors":"R. Vázquez-Medina, A. Díaz-Méndez, M. Cruz‐Irisson, J. L. Del-Río-Correa, J. López-Hernández","doi":"10.1109/MWSCAS.2009.5236131","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236131","url":null,"abstract":"In this paper, the Birkhoff's Ergodic Theorem, mixing property of the one-dimensional maps, strong convergence criterion and Kullbak-Leibler divergence are applied in order to design chaotic analogical noise generators using MOS QT Circuits, which are governed by one-dimensional chaotic maps. In this work an analogical circuit is used, which have a structure of transistors MOS that operates in current-mode and that uses the transconductance linear principle.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"372 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122854916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236083
S. Ghetmiri, C. Salama
This paper discusses the design and characterization of a track-and-hold amplifier (THA) and a comparator which are the essential building blocks of an 8bit, 12.5GS/s folding-interpolating analog to digital converter (ADC) with a 3GHz bandwidth. The circuits are implemented in a 0.25µm, 190GHz SiGe BiCMOS process. The THA occupies an area of 0.5mm2. It features a SNDR of 47dB or 7.5bits ENOB for a 3GHz bandwidth, a hold time of 21ps with a droop rate of 11mV/80ps and a power dissipation of 230mW from a 3.3V supply. The comparator occupies an area of 0.38mm2 and exhibits an input sensitivity of ±2mV, an input offset voltage of 1.5mV, latch and recovery times of 19 and 21ps respectively and a power dissipation of 150mW from a 3.3V supply.
{"title":"Track-and-hold and comparator for a 12.5GS/s, 8bit ADC","authors":"S. Ghetmiri, C. Salama","doi":"10.1109/MWSCAS.2009.5236083","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236083","url":null,"abstract":"This paper discusses the design and characterization of a track-and-hold amplifier (THA) and a comparator which are the essential building blocks of an 8bit, 12.5GS/s folding-interpolating analog to digital converter (ADC) with a 3GHz bandwidth. The circuits are implemented in a 0.25µm, 190GHz SiGe BiCMOS process. The THA occupies an area of 0.5mm2. It features a SNDR of 47dB or 7.5bits ENOB for a 3GHz bandwidth, a hold time of 21ps with a droop rate of 11mV/80ps and a power dissipation of 230mW from a 3.3V supply. The comparator occupies an area of 0.38mm2 and exhibits an input sensitivity of ±2mV, an input offset voltage of 1.5mV, latch and recovery times of 19 and 21ps respectively and a power dissipation of 150mW from a 3.3V supply.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114267444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235968
N. M. Nayeem, A. Hossain, Mutasimul Haque, Lafifa Jamal, H. M. H. Babu
This paper presents a novel design of sequential division circuit using reversible logic, which is a promising research area nowadays. The proposed hardware has its application in the design of reversible arithmetic logic unit. In order to show the efficiency, lower bounds of the proposed design are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement division hardware. As the works in the field of reversible logic has only started to bloom, the contribution of this paper will engender a new thread of research in the field of reversible division circuit.
{"title":"Novel reversible division hardware","authors":"N. M. Nayeem, A. Hossain, Mutasimul Haque, Lafifa Jamal, H. M. H. Babu","doi":"10.1109/MWSCAS.2009.5235968","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235968","url":null,"abstract":"This paper presents a novel design of sequential division circuit using reversible logic, which is a promising research area nowadays. The proposed hardware has its application in the design of reversible arithmetic logic unit. In order to show the efficiency, lower bounds of the proposed design are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement division hardware. As the works in the field of reversible logic has only started to bloom, the contribution of this paper will engender a new thread of research in the field of reversible division circuit.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121890665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235909
E. Arroyo-Huerta, A. Díaz-Méndez, J. Ramírez-Cortés, J. C. S. Garcia
In this work an adaptive impedance matching scheme for 2.4GHz wireless communication, based on fuzzy control, is proposed. For that purpose, a two-port passive matching network controlled by a zero-order Takagi-Sugeno-Kang fuzzy controller is used, allowing the system to iterate until the matching point is reached. Several experiments using the fuzzy controller coupled to π, T, and L impedance matching networks are presented. Preliminary results derived from MATLAB 7.1 simulations of the described algorithm, and a comparison with a least mean square (LMS) impedance matching approach, are discussed.
{"title":"An adaptive impedance matching approach based on fuzzy control","authors":"E. Arroyo-Huerta, A. Díaz-Méndez, J. Ramírez-Cortés, J. C. S. Garcia","doi":"10.1109/MWSCAS.2009.5235909","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235909","url":null,"abstract":"In this work an adaptive impedance matching scheme for 2.4GHz wireless communication, based on fuzzy control, is proposed. For that purpose, a two-port passive matching network controlled by a zero-order Takagi-Sugeno-Kang fuzzy controller is used, allowing the system to iterate until the matching point is reached. Several experiments using the fuzzy controller coupled to π, T, and L impedance matching networks are presented. Preliminary results derived from MATLAB 7.1 simulations of the described algorithm, and a comparison with a least mean square (LMS) impedance matching approach, are discussed.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116829882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235897
M. Jimenez-Salinas, Francisco Garcia-Ugald
We present a watermarking approach using a directional multiresolution transform named contourlet. Contourlet transform offers a flexible image decomposition at various directions in multiple scales with flexible ratios, then it is easier to determine image areas which are less sensitive to human eye. We combine an spread spectrum scheme with a convolutional coding scheme to improve the capacity of watermark embedded through the host signal. We present some experimental results of our algorithm tested to common signal processing operation, which could be intentional or unintentional.
{"title":"Improvement in spread spectrum watermarking through convolutional codes","authors":"M. Jimenez-Salinas, Francisco Garcia-Ugald","doi":"10.1109/MWSCAS.2009.5235897","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235897","url":null,"abstract":"We present a watermarking approach using a directional multiresolution transform named contourlet. Contourlet transform offers a flexible image decomposition at various directions in multiple scales with flexible ratios, then it is easier to determine image areas which are less sensitive to human eye. We combine an spread spectrum scheme with a convolutional coding scheme to improve the capacity of watermark embedded through the host signal. We present some experimental results of our algorithm tested to common signal processing operation, which could be intentional or unintentional.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128320930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235967
Young Bok Kim, Yong-Bin Kim, F. Lombardi
Carbon nanotubes with their superior properties have proved to be a potential alternative device to CMOS. In this paper, circuit optimization methods for high performance and low power CNFEFT circuit are proposed. The proposed design methods for CNTFET circuit address how to decide the optimum CNTFET parameters such as pitch, diameter, number of CNTs (Carbon Nano Tube), optimum fan-out factor and logical efforts to deliver the minimum power-delay product. The proposed method makes it possible to accomplish 56% dynamic power reduction and 22% less delay by optimizing the pitch, number of CNTs, fan-out factor, and logical efforts compared to the circuits that are not optimized and screening effects are ignored.
{"title":"A novel design methodology to optimize the speed and power of the CNTFET circuits","authors":"Young Bok Kim, Yong-Bin Kim, F. Lombardi","doi":"10.1109/MWSCAS.2009.5235967","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235967","url":null,"abstract":"Carbon nanotubes with their superior properties have proved to be a potential alternative device to CMOS. In this paper, circuit optimization methods for high performance and low power CNFEFT circuit are proposed. The proposed design methods for CNTFET circuit address how to decide the optimum CNTFET parameters such as pitch, diameter, number of CNTs (Carbon Nano Tube), optimum fan-out factor and logical efforts to deliver the minimum power-delay product. The proposed method makes it possible to accomplish 56% dynamic power reduction and 22% less delay by optimizing the pitch, number of CNTs, fan-out factor, and logical efforts compared to the circuits that are not optimized and screening effects are ignored.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128662801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236128
Yen-Ting Wang, R. Geiger, Shu-Chuan Huang
A new voltage reference with output dependent upon the threshold voltage of an NMOS transistor is introduced. A low temperature coefficient is achieved by using a pn-junction PTAT current generator to compensate for the negative temperature coefficient of the threshold voltage. Implemented in a standard 0.6µm CMOS process with an output of 1.67V, it has a temperature coefficient of 4.9ppm/°C over a 195 °C range.
{"title":"Threshold-based voltage reference with pn- junction temperature compensation","authors":"Yen-Ting Wang, R. Geiger, Shu-Chuan Huang","doi":"10.1109/MWSCAS.2009.5236128","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236128","url":null,"abstract":"A new voltage reference with output dependent upon the threshold voltage of an NMOS transistor is introduced. A low temperature coefficient is achieved by using a pn-junction PTAT current generator to compensate for the negative temperature coefficient of the threshold voltage. Implemented in a standard 0.6µm CMOS process with an output of 1.67V, it has a temperature coefficient of 4.9ppm/°C over a 195 °C range.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129089068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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