A 10bit 1.1V 130MS/s 0.125mm2 pipeline ADC for flat-panel display applications in 65nm CMOS

Abstract

This paper presents the design and implementation of a low-voltage low-power high speed pipeline analog-to-digital converter (ADC) for flat-panel display application fabricated in a standard digital 65nm CMOS technology. The ADC does not use a dedicated sample-and-hold (S&H) stage and is built by means of the cascade of 8 pipeline stages and a 2-bit flash ADC. Operational amplifier sharing technique is applied in order to reduce power consumption. Nested cascoded miller compensation technique is used to optimize speed and power of the first and second stage. Performance of 56.5dB SNDR at 5MHz and 50dB at 85MHz input frequency is obtained at 130MS/s for full-scale. The occupied silicon area is 0.125mm2, and the power consumption of 33mW from a 1.1V supply.