Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201338
Marta Blaszczyk, R. Guinee
In this paper the experimental validation of a novel, modified double scroll chaotic attractor circuit, employed as a true random binary generator (TRBG) is presented. The double scroll attractor is modeled on a chaotic circuit for nonlinear operation leading to stochastic like behavior. The output from the chaotic circuit which is a correlated binary sequence is scrambled with a pseudo random binary sequence generator (PRBSG) topology to yield a true random binary source for key stream generation. The modified chaotic circuit has been first modeled in PSpice software and its state space formulation was implemented in Matlab and Simulink software to gauge simulation accuracy and potential as a cryptographic module via statistical testing. The randomness attributes of the modified generator, obtained from both the PSpice state space model along with the hardware implementation, using the PRBSG de-correlator were successfully tested by the well known NIST Test Suite and Diehard Test Set for statistical validation. A physical TRBG has been constructed on the basis of the proposed PRBSG modification with all statistical tests successfully passed confirming theoretical expectations.
{"title":"Experimental validation of a novel chaotic circuit for true random binary digit generation in cryptographic module application","authors":"Marta Blaszczyk, R. Guinee","doi":"10.1109/RME.2009.5201338","DOIUrl":"https://doi.org/10.1109/RME.2009.5201338","url":null,"abstract":"In this paper the experimental validation of a novel, modified double scroll chaotic attractor circuit, employed as a true random binary generator (TRBG) is presented. The double scroll attractor is modeled on a chaotic circuit for nonlinear operation leading to stochastic like behavior. The output from the chaotic circuit which is a correlated binary sequence is scrambled with a pseudo random binary sequence generator (PRBSG) topology to yield a true random binary source for key stream generation. The modified chaotic circuit has been first modeled in PSpice software and its state space formulation was implemented in Matlab and Simulink software to gauge simulation accuracy and potential as a cryptographic module via statistical testing. The randomness attributes of the modified generator, obtained from both the PSpice state space model along with the hardware implementation, using the PRBSG de-correlator were successfully tested by the well known NIST Test Suite and Diehard Test Set for statistical validation. A physical TRBG has been constructed on the basis of the proposed PRBSG modification with all statistical tests successfully passed confirming theoretical expectations.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125165755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201369
M. Ferri, D. Pinna, E. Dallago, P. Malcovati
In this paper we present an integrated solar energy scavenger realized in a 0.35 μm CMOS technology. The proposed system collects solar energy from the environment through integrated diodes, accumulates it and, delivers it to the load when it is enough to allow proper operation of the CMOS circuitry. The proposed system is suitable for discrete-time regime applications, such as sensor network nodes or, generally, systems that require power supply periodically for short time slots. In order to properly design the system, we developed a model of the integrated solar cell on the basis of measurement data extracted from a test chip. The power management circuit, including a charge pump a comparator and a linear voltage regulator, has been extensively simulated.
{"title":"A 0.35μm CMOS Solar energy scavenger with power storage management system","authors":"M. Ferri, D. Pinna, E. Dallago, P. Malcovati","doi":"10.1109/RME.2009.5201369","DOIUrl":"https://doi.org/10.1109/RME.2009.5201369","url":null,"abstract":"In this paper we present an integrated solar energy scavenger realized in a 0.35 μm CMOS technology. The proposed system collects solar energy from the environment through integrated diodes, accumulates it and, delivers it to the load when it is enough to allow proper operation of the CMOS circuitry. The proposed system is suitable for discrete-time regime applications, such as sensor network nodes or, generally, systems that require power supply periodically for short time slots. In order to properly design the system, we developed a model of the integrated solar cell on the basis of measurement data extracted from a test chip. The power management circuit, including a charge pump a comparator and a linear voltage regulator, has been extensively simulated.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115048005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201351
V. Peikert, A. Schenk
This paper presents a first analysis of a new general fixed point iteration of the Boltzmann transport equation. The scheme is based on a recent theory on Inverse Scattering Operators. Due to the fact that the implementation of this scheme is extremely involved, the expansion is truncated after the second iteration as a start. Comparisons with Monte Carlo simulations verify that the second iteration step gives sufficient corrections to the equilibrium distribution in bulk silicon, if the external field is not too large. However, it turns out that the second iteration is not sufficient to address inhomogeneous semiconductors. One reason is that a term containing the built-in electric field is not compensated in this order. Moreover, even in regions with low electric field and with small gradients of the quasi-Fermi level the second-order solution deviates notably from Monte Carlo simulations. Although this scheme has a lot of potential for TCAD applications, the adaptability is not straight-forward and further analysis of higher order terms is necessary.
{"title":"A first analysis of a new fixed point iteration of the Boltzmann equation: Application to TCAD","authors":"V. Peikert, A. Schenk","doi":"10.1109/RME.2009.5201351","DOIUrl":"https://doi.org/10.1109/RME.2009.5201351","url":null,"abstract":"This paper presents a first analysis of a new general fixed point iteration of the Boltzmann transport equation. The scheme is based on a recent theory on Inverse Scattering Operators. Due to the fact that the implementation of this scheme is extremely involved, the expansion is truncated after the second iteration as a start. Comparisons with Monte Carlo simulations verify that the second iteration step gives sufficient corrections to the equilibrium distribution in bulk silicon, if the external field is not too large. However, it turns out that the second iteration is not sufficient to address inhomogeneous semiconductors. One reason is that a term containing the built-in electric field is not compensated in this order. Moreover, even in regions with low electric field and with small gradients of the quasi-Fermi level the second-order solution deviates notably from Monte Carlo simulations. Although this scheme has a lot of potential for TCAD applications, the adaptability is not straight-forward and further analysis of higher order terms is necessary.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129264347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201333
I. Pachnis, A. Demosthenous, N. Donaldson
Since the introduction of the quasi-tripole amplifier configuration in the mid-70s for the purpose of long-term recording of neural signals from peripheral nerves, research efforts are now being focused in using peripheral nerve signals as control inputs to neural prostheses. This paper gives an overview of the most important neural recording tripolar configurations, and explores the idea of modeling the polarization impedance of electrodes using branched ladder networks to achieve adaptive passive neutralization of myoeletric interference.
{"title":"Interference reduction techniques in neural recording tripoles: An overview","authors":"I. Pachnis, A. Demosthenous, N. Donaldson","doi":"10.1109/RME.2009.5201333","DOIUrl":"https://doi.org/10.1109/RME.2009.5201333","url":null,"abstract":"Since the introduction of the quasi-tripole amplifier configuration in the mid-70s for the purpose of long-term recording of neural signals from peripheral nerves, research efforts are now being focused in using peripheral nerve signals as control inputs to neural prostheses. This paper gives an overview of the most important neural recording tripolar configurations, and explores the idea of modeling the polarization impedance of electrodes using branched ladder networks to achieve adaptive passive neutralization of myoeletric interference.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116296989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201305
D. Ferenci, M. Grozing, M. Berroth
A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2mm2 while the ADC core area is 0.16mm2.
{"title":"Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS","authors":"D. Ferenci, M. Grozing, M. Berroth","doi":"10.1109/RME.2009.5201305","DOIUrl":"https://doi.org/10.1109/RME.2009.5201305","url":null,"abstract":"A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2mm2 while the ADC core area is 0.16mm2.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131921859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201341
I. Myderrizi, A. Zeki
A behavioral model is developed for segmented current-steering DAC. System is modeled by constructing a set of subsystems in SIMULINK® environment. To validate the model a 12-bit segmented current-steering DAC is modeled and performance characteristics are investigated for the worst case operation of the system. Simulation results confirm the accuracy of the model.
{"title":"Behavioral model of segmented current-steering DAC by using SIMULINK®","authors":"I. Myderrizi, A. Zeki","doi":"10.1109/RME.2009.5201341","DOIUrl":"https://doi.org/10.1109/RME.2009.5201341","url":null,"abstract":"A behavioral model is developed for segmented current-steering DAC. System is modeled by constructing a set of subsystems in SIMULINK® environment. To validate the model a 12-bit segmented current-steering DAC is modeled and performance characteristics are investigated for the worst case operation of the system. Simulation results confirm the accuracy of the model.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134329072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201297
Nicolas Pillin, C. Dehollain, M. Declercq
A model is proposed to describe the fundamental read range limitation due to the local oscillator phase noise in the reader, in IF-based, far-field RFID systems using amplitude-shift keying backscatter modulation. The relation between the system parameters (such as the data transfer rate) and the read range is discussed. The model is validated by measurements done on two different laboratory tag-reader systems.
{"title":"Read range limitation in IF-based far-field RFID using ASK backscatter modulation","authors":"Nicolas Pillin, C. Dehollain, M. Declercq","doi":"10.1109/RME.2009.5201297","DOIUrl":"https://doi.org/10.1109/RME.2009.5201297","url":null,"abstract":"A model is proposed to describe the fundamental read range limitation due to the local oscillator phase noise in the reader, in IF-based, far-field RFID systems using amplitude-shift keying backscatter modulation. The relation between the system parameters (such as the data transfer rate) and the read range is discussed. The model is validated by measurements done on two different laboratory tag-reader systems.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114822686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201309
D. Ponton, G. Knoblinger, A. Roithmeier, M. Tiebout, M. Fulde, P. Palestri
This paper deals with the design of LC Voltage Controlled Oscillator (LC-VCO) for GSM applications, implemented in a state-of-the-art 32nm Planar CMOS technology. A standard VCO is compared with a topology featuring tail decoupling, which, to best of our knowledge, is used for the first time for a wide tuning-range application (i.e. 700MHz centered at 3.65GHz). The Decoupled VCO significantly reduces the Phase-Noise, up to 9dB, by lowering the impact of the flicker noise introduced by the switching-pair on the 1/ f 3 region, with comparable current consumption and tuning-range with respect to the standard VCO.
{"title":"Reduction of up-converted flicker noise in differential LC-VCO designed in 32nm CMOS technology","authors":"D. Ponton, G. Knoblinger, A. Roithmeier, M. Tiebout, M. Fulde, P. Palestri","doi":"10.1109/RME.2009.5201309","DOIUrl":"https://doi.org/10.1109/RME.2009.5201309","url":null,"abstract":"This paper deals with the design of LC Voltage Controlled Oscillator (LC-VCO) for GSM applications, implemented in a state-of-the-art 32nm Planar CMOS technology. A standard VCO is compared with a topology featuring tail decoupling, which, to best of our knowledge, is used for the first time for a wide tuning-range application (i.e. 700MHz centered at 3.65GHz). The Decoupled VCO significantly reduces the Phase-Noise, up to 9dB, by lowering the impact of the flicker noise introduced by the switching-pair on the 1/ f 3 region, with comparable current consumption and tuning-range with respect to the standard VCO.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114709651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201315
E. Volpi, L. Fanucci, F. D'Ascoli
The design of a high voltage fully differential driver in a 0.18 µm Bipolar-CMOS-DMOS (BCD) technology for the actuation of a double axis scanning micromirror is presented. The proposed circuit has a driving voltage capability up to 25 V and a low Total Harmonic Distortion in order to prevent the excitation of unwanted micromirror's higher resonating modes. This design features a low voltage input stage and a programmable output common mode voltage. After a description of the circuit, results of simulations performed with an equivalent electrical model of the micromirror are presented.
{"title":"Design of a high voltage fully differential driver for a double axis scanning micromirror","authors":"E. Volpi, L. Fanucci, F. D'Ascoli","doi":"10.1109/RME.2009.5201315","DOIUrl":"https://doi.org/10.1109/RME.2009.5201315","url":null,"abstract":"The design of a high voltage fully differential driver in a 0.18 µm Bipolar-CMOS-DMOS (BCD) technology for the actuation of a double axis scanning micromirror is presented. The proposed circuit has a driving voltage capability up to 25 V and a low Total Harmonic Distortion in order to prevent the excitation of unwanted micromirror's higher resonating modes. This design features a low voltage input stage and a programmable output common mode voltage. After a description of the circuit, results of simulations performed with an equivalent electrical model of the micromirror are presented.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123586369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201343
V. Stornelli, G. Leuzzi
The frequency-domain Spectral Balance technique has been demonstrated to be a viable alternative to the mixeddomain Harmonic Balance technique. In this work a frequencydomain Fourier series expansion and space-domain polynomial expansion of the physical quantities inside the semiconductor for the solution of steady-state nonlinear differential equations is applied to the physical analysis of multifinger MOSFET devices in linear and nonlinear regime and coupled to a commercial electromagnetic solver. The method allows a really fast CAD analysis both in DC and RF periodic regime especially when global modeling is required. A quasi-2D hydrodynamic formulation is given for a 0.35µm gate length with 10µm periphery three finger MOSFET; results are compared to those of a standard physical time-domain, a Harmonic Balance and Spectral Balance for time comparison. Moreover S-parameter comparisons with a commercial CAD tools with a compact model for circuit analysis are also given.
{"title":"Global modeling of multifinger MOSFETs with SB-SP combined analysis","authors":"V. Stornelli, G. Leuzzi","doi":"10.1109/RME.2009.5201343","DOIUrl":"https://doi.org/10.1109/RME.2009.5201343","url":null,"abstract":"The frequency-domain Spectral Balance technique has been demonstrated to be a viable alternative to the mixeddomain Harmonic Balance technique. In this work a frequencydomain Fourier series expansion and space-domain polynomial expansion of the physical quantities inside the semiconductor for the solution of steady-state nonlinear differential equations is applied to the physical analysis of multifinger MOSFET devices in linear and nonlinear regime and coupled to a commercial electromagnetic solver. The method allows a really fast CAD analysis both in DC and RF periodic regime especially when global modeling is required. A quasi-2D hydrodynamic formulation is given for a 0.35µm gate length with 10µm periphery three finger MOSFET; results are compared to those of a standard physical time-domain, a Harmonic Balance and Spectral Balance for time comparison. Moreover S-parameter comparisons with a commercial CAD tools with a compact model for circuit analysis are also given.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127238471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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