A Soft Error Resilient Low Leakage SRAM Cell Design

Abstract

Semiconductor industry has been aggressively following the Moore's Law ever since its was proposed in the late sixties in its pursuit for smaller device sizes and higher performance metrics. However, this vigorous scaling has brought in several scaling induced side effects like single event upsets into the technology regime. SRAMs are highly susceptible to such upsets since they are designed at minimum device sizes to keep the on-chip memory density high. This paper presents a novel SEU-hardened SRAM cell employing single bitline. The proposed cell is 4 times more immune than a standard 6T-SRAM cell and also achieves 68% reduction in bitline leakage.