Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. High-volume diagnosis has become crucial for yield learning. The backbone of any diagnosis algorithm is the test set in use. Application of test sets for high-volume testing is typically done in test data compression environment to reduce the test time and also the amount of data stored on the tester. For high-volume diagnosis, it is essential to use test sets having high diagnostic power in compression environment. In this work, a novel method has been proposed which combines test data compression and diagnostic power improvement algorithms. Selective Huffman coding is used as the basic test data compression scheme. To improve diagnostic power of a test set we make use of filling algorithms designed to increase the diagnostic ability of the test set.
{"title":"An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets","authors":"Srinivasa Shashank Nuthakki, S. Chattopadhyay","doi":"10.1109/ATS.2015.33","DOIUrl":"https://doi.org/10.1109/ATS.2015.33","url":null,"abstract":"Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. High-volume diagnosis has become crucial for yield learning. The backbone of any diagnosis algorithm is the test set in use. Application of test sets for high-volume testing is typically done in test data compression environment to reduce the test time and also the amount of data stored on the tester. For high-volume diagnosis, it is essential to use test sets having high diagnostic power in compression environment. In this work, a novel method has been proposed which combines test data compression and diagnostic power improvement algorithms. Selective Huffman coding is used as the basic test data compression scheme. To improve diagnostic power of a test set we make use of filling algorithms designed to increase the diagnostic ability of the test set.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126843106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Detecting the defects inside the CMOS cells, especially the stuck-open faults, has gained a lot of attentions in recent years. It had been shown the test set generated by using the transition fault model is not sufficient to detect the stuck-open faults. In this paper, we propose an enhanced transition fault model, named cell transition, to improve the quality of the transition test set on detecting the stuck-open faults inside the CMOS cells. The fault sites targeted by the proposed model are placed at the cell boundary in order to keep the fault population similar to the transition fault model. Experimental results demonstrate the cell transition test set detects more stuck-open faults than the transition test set while the test coverage achieved for the transition faults is close to that obtained by the transition test set. Moreover, the number of generated tests is slightly higher than the transition test set.
{"title":"On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults","authors":"X. Lin, Wu-Tung Cheng, J. Rajski","doi":"10.1109/ATS.2015.24","DOIUrl":"https://doi.org/10.1109/ATS.2015.24","url":null,"abstract":"Detecting the defects inside the CMOS cells, especially the stuck-open faults, has gained a lot of attentions in recent years. It had been shown the test set generated by using the transition fault model is not sufficient to detect the stuck-open faults. In this paper, we propose an enhanced transition fault model, named cell transition, to improve the quality of the transition test set on detecting the stuck-open faults inside the CMOS cells. The fault sites targeted by the proposed model are placed at the cell boundary in order to keep the fault population similar to the transition fault model. Experimental results demonstrate the cell transition test set detects more stuck-open faults than the transition test set while the test coverage achieved for the transition faults is close to that obtained by the transition test set. Moreover, the number of generated tests is slightly higher than the transition test set.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128115823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li
With the growth of cloud computing, security and privacy is becoming more and more important. Timing channel attack is one of the most remarkable security threads for memory controllers due to competition for shared resources. However, the existing protection strategies that ensure the deterministic of memory accesses by dividing bandwidth introduce great latency and performance degradation. This paper proposes a refresh hiding approach that adjusts the refresh operations to multiplex refresh time with additional latency introduced by those bandwidth division strategies. The experiment results show refresh hiding can reduce more than 20% of program runtime, and it will be more efficient as DRAM density increases.
{"title":"A Lightweight Timing Channel Protection for Shared Memory Controllers","authors":"Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li","doi":"10.1109/ATS.2015.17","DOIUrl":"https://doi.org/10.1109/ATS.2015.17","url":null,"abstract":"With the growth of cloud computing, security and privacy is becoming more and more important. Timing channel attack is one of the most remarkable security threads for memory controllers due to competition for shared resources. However, the existing protection strategies that ensure the deterministic of memory accesses by dividing bandwidth introduce great latency and performance degradation. This paper proposes a refresh hiding approach that adjusts the refresh operations to multiplex refresh time with additional latency introduced by those bandwidth division strategies. The experiment results show refresh hiding can reduce more than 20% of program runtime, and it will be more efficient as DRAM density increases.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125860504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang
Parallelism is one promising solution to accelerating the test pattern generation (TPG) process, several recent works also show that parallel TPG can reduce the test pattern count. However, today's parallel TPG's are mostly non-deterministic, i.e., the generated test set is timing and resource dependent, this complicates the debug process and may degrade the user experience. In this paper, we propose a multi-threading parallel test pattern generator that is both deterministic and incurs zero test inflation. Called SDC-TPG, the proposed parallel TPG relies on synchronized dynamic compaction (SDC) to generate the same test pattern set as the conventional serial TPG with dynamic compaction regardless of the thread timing and the thread count. Furthermore, an early primary fault TPG strategy is proposed to reduce the thread idle times and improve the speedup. Simulation results show that SDC-TPG achieves an average speedup of six with eight threads.
{"title":"SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator","authors":"Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang","doi":"10.1109/ATS.2015.15","DOIUrl":"https://doi.org/10.1109/ATS.2015.15","url":null,"abstract":"Parallelism is one promising solution to accelerating the test pattern generation (TPG) process, several recent works also show that parallel TPG can reduce the test pattern count. However, today's parallel TPG's are mostly non-deterministic, i.e., the generated test set is timing and resource dependent, this complicates the debug process and may degrade the user experience. In this paper, we propose a multi-threading parallel test pattern generator that is both deterministic and incurs zero test inflation. Called SDC-TPG, the proposed parallel TPG relies on synchronized dynamic compaction (SDC) to generate the same test pattern set as the conventional serial TPG with dynamic compaction regardless of the thread timing and the thread count. Furthermore, an early primary fault TPG strategy is proposed to reduce the thread idle times and improve the speedup. Simulation results show that SDC-TPG achieves an average speedup of six with eight threads.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129424436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, H. Fujiwara
In recent years, various high-level test synthesis methods for data paths have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches assume that controllers and data paths are isolated from each other, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually decreases the testability. To resolve this problem, an approach that augments a controller by adding extra control functions to make a data path easily testable was proposed. However, the approach cannot always succeed in generating test sequences with high fault coverage if a general ATPG tool is used without knowing any information of augmented control functions. In this paper, we introduce "easily testable functional time expansion models for data paths", and propose a test generation method for data paths using easily testable functional time expansion models and controller augmentation such that easily testable functional time expansion models are controllable. Experimental results show the effectiveness of the proposed method for high level synthesis benchmark circuits.
{"title":"A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation","authors":"Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, H. Fujiwara","doi":"10.1109/ATS.2015.14","DOIUrl":"https://doi.org/10.1109/ATS.2015.14","url":null,"abstract":"In recent years, various high-level test synthesis methods for data paths have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches assume that controllers and data paths are isolated from each other, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually decreases the testability. To resolve this problem, an approach that augments a controller by adding extra control functions to make a data path easily testable was proposed. However, the approach cannot always succeed in generating test sequences with high fault coverage if a general ATPG tool is used without knowing any information of augmented control functions. In this paper, we introduce \"easily testable functional time expansion models for data paths\", and propose a test generation method for data paths using easily testable functional time expansion models and controller augmentation such that easily testable functional time expansion models are controllable. Experimental results show the effectiveness of the proposed method for high level synthesis benchmark circuits.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123030879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sukrat Gupta, Neel Gala, G. Madhusudan, V. Kamakoti
Deeply scaled CMOS circuits are vulnerable to soft and hard errors. These errors pose reliability concerns, especially for systems used in radiation-prone environments like space and nuclear applications. This paper presents SHAKTI-F, a RISC-V based SEE-tolerant micro-processor architecture that provides a solution to the reliability issues mentioned above. The proposed architecture uses error correcting codes (ECC) to tolerate errors in registers and memories, while it employs a combination of space and time redundancy based techniques to tolerate errors in the ALU. Two novel re-computation techniques for detecting errors for the addition/subtraction and multiplication modules are proposed. The scheme also identifies parts of the circuitry that need to be radiation hardened thus providing a total protection to SEEs. The proposed scheme provides fine-grain error detection capability that help in localization of the error to a specific functional unit and isolating the same, rather than the entire processor or a large module within a processor. This provides a graceful degradation and/or fail-safe shutdown capability to the processor. The HDL model of the processor was validated by simulating it with randomly induced SEEs. The proposed scheme adds an extra penalty of only 20% on the core area and 25% penalty on the performance when compared with conventional systems. This is very less when compared to the penalty incurred by employing schemes including double modular and triple modular redundancy. Interestingly, there is a 45% reduction in power consumption due to introduction of fault tolerance. The resulting system runs at 330 MHz on a 55nm technology node, which is sufficient for the class of applications these cores are utilized for.
{"title":"SHAKTI-F: A Fault Tolerant Microprocessor Architecture","authors":"Sukrat Gupta, Neel Gala, G. Madhusudan, V. Kamakoti","doi":"10.1109/ATS.2015.35","DOIUrl":"https://doi.org/10.1109/ATS.2015.35","url":null,"abstract":"Deeply scaled CMOS circuits are vulnerable to soft and hard errors. These errors pose reliability concerns, especially for systems used in radiation-prone environments like space and nuclear applications. This paper presents SHAKTI-F, a RISC-V based SEE-tolerant micro-processor architecture that provides a solution to the reliability issues mentioned above. The proposed architecture uses error correcting codes (ECC) to tolerate errors in registers and memories, while it employs a combination of space and time redundancy based techniques to tolerate errors in the ALU. Two novel re-computation techniques for detecting errors for the addition/subtraction and multiplication modules are proposed. The scheme also identifies parts of the circuitry that need to be radiation hardened thus providing a total protection to SEEs. The proposed scheme provides fine-grain error detection capability that help in localization of the error to a specific functional unit and isolating the same, rather than the entire processor or a large module within a processor. This provides a graceful degradation and/or fail-safe shutdown capability to the processor. The HDL model of the processor was validated by simulating it with randomly induced SEEs. The proposed scheme adds an extra penalty of only 20% on the core area and 25% penalty on the performance when compared with conventional systems. This is very less when compared to the penalty incurred by employing schemes including double modular and triple modular redundancy. Interestingly, there is a 45% reduction in power consumption due to introduction of fault tolerance. The resulting system runs at 330 MHz on a 55nm technology node, which is sufficient for the class of applications these cores are utilized for.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133088083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A large amount of time and effort must be spent to ensure the correctness of a digital design. Although many Computer Aided Design (CAD) solutions have been provided to enhance efficiency of existing debugging approaches, they are suffering from shortage of efficient automatic correction mechanisms. In this paper, we introduce an in-circuit mutation technique for correcting design bugs in digital designs. The aim of this work is reducing correction time by connecting primitive gates into inputs of 6-to-1 multiplexers in the place of potential bugs and utilizing satisfiability (SAT) engine for choosing the correct gates. The empirical results demonstrate that our proposed method can correct multiple bugs in a design by targeting gate replacements and wires exchanges efficiently. Average improvements in terms of the runtime and success rate in correction for combinational circuits in comparison with the latest the existing method are 3.4× and 11.5%, respectively. These results for sequential circuits are 3.8× and 17% respectively.
{"title":"In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms","authors":"Payman Behnam, B. Alizadeh","doi":"10.1109/ATS.2015.41","DOIUrl":"https://doi.org/10.1109/ATS.2015.41","url":null,"abstract":"A large amount of time and effort must be spent to ensure the correctness of a digital design. Although many Computer Aided Design (CAD) solutions have been provided to enhance efficiency of existing debugging approaches, they are suffering from shortage of efficient automatic correction mechanisms. In this paper, we introduce an in-circuit mutation technique for correcting design bugs in digital designs. The aim of this work is reducing correction time by connecting primitive gates into inputs of 6-to-1 multiplexers in the place of potential bugs and utilizing satisfiability (SAT) engine for choosing the correct gates. The empirical results demonstrate that our proposed method can correct multiple bugs in a design by targeting gate replacements and wires exchanges efficiently. Average improvements in terms of the runtime and success rate in correction for combinational circuits in comparison with the latest the existing method are 3.4× and 11.5%, respectively. These results for sequential circuits are 3.8× and 17% respectively.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125032884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ishida, T. Nakura, Akira Matsukawa, R. Ikeno, K. Asada
This paper proposes a method for analyzing the power supply impedance at an on-chip power supply node in the device under test. The proposed method is based on an on-chip power measurement of a power supply voltage fluctuation with sweeping the frequency of the on-chip current load which sinks a square wave current, not sinusoidal. The method can extract the frequency characteristics of not only the magnitude but also the phase characteristic of the power supply impedance. Experimental results based on SPICE simulations proved that the proposed method can accurately measure the frequency characteristic of the power supply impedance. It is also confirmed that the extracted power supply impedance characteristics gives quite similar transient voltage waveforms to the target waveforms.
{"title":"A Technique for Analyzing On-Chip Power Supply Impedance","authors":"M. Ishida, T. Nakura, Akira Matsukawa, R. Ikeno, K. Asada","doi":"10.1109/ATS.2015.40","DOIUrl":"https://doi.org/10.1109/ATS.2015.40","url":null,"abstract":"This paper proposes a method for analyzing the power supply impedance at an on-chip power supply node in the device under test. The proposed method is based on an on-chip power measurement of a power supply voltage fluctuation with sweeping the frequency of the on-chip current load which sinks a square wave current, not sinusoidal. The method can extract the frequency characteristics of not only the magnitude but also the phase characteristic of the power supply impedance. Experimental results based on SPICE simulations proved that the proposed method can accurately measure the frequency characteristic of the power supply impedance. It is also confirmed that the extracted power supply impedance characteristics gives quite similar transient voltage waveforms to the target waveforms.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125065397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diagnosis of integrated circuits is an arduous process. Tools are needed which aid developers locating circuit's faulty parts faster. In this work path delay faults are considered. A simulation based diagnosis algorithm using diagnostic test patterns is introduced for locating the cause of the delay fault. Initial paths are segmented to improve the diagnosis accuracy. For each segment, additional diagnostic test patterns are generated using a solver for Boolean Satisfiability. The experimental results show that a significant improvement of the diagnostic accuracy is achievable with our approach.
{"title":"Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation","authors":"Tino Flenker, André Sülflow, G. Fey","doi":"10.1109/ATS.2015.32","DOIUrl":"https://doi.org/10.1109/ATS.2015.32","url":null,"abstract":"Diagnosis of integrated circuits is an arduous process. Tools are needed which aid developers locating circuit's faulty parts faster. In this work path delay faults are considered. A simulation based diagnosis algorithm using diagnostic test patterns is introduced for locating the cause of the delay fault. Initial paths are segmented to improve the diagnosis accuracy. For each segment, additional diagnostic test patterns are generated using a solver for Boolean Satisfiability. The experimental results show that a significant improvement of the diagnostic accuracy is achievable with our approach.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"8 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123279632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new power-aware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time. Since enabling only a subset of scan flip-flops to capture test responses in one cycle compromises the fault coverage, we propose a new method to reduce the fault coverage loss. First, we use a more accurate notion, spoiled nodes, instead of violation edges used in previous works to analyse the ependency of flip-flops, then we use simulated annealing(SA) mechanism to find the best combination of these flip-flops while considering the clock trees' impact. To the best of our knowledge, this is the first work to make shift and capture power in a controllable way with minimum fault coverage loss, small test-data volume and no extra hardware overhead for at-speed transition fault test. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed method.
{"title":"A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test","authors":"Z. Jiang, D. Xiang, Kele Shen","doi":"10.1109/ATS.2015.9","DOIUrl":"https://doi.org/10.1109/ATS.2015.9","url":null,"abstract":"The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new power-aware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time. Since enabling only a subset of scan flip-flops to capture test responses in one cycle compromises the fault coverage, we propose a new method to reduce the fault coverage loss. First, we use a more accurate notion, spoiled nodes, instead of violation edges used in previous works to analyse the ependency of flip-flops, then we use simulated annealing(SA) mechanism to find the best combination of these flip-flops while considering the clock trees' impact. To the best of our knowledge, this is the first work to make shift and capture power in a controllable way with minimum fault coverage loss, small test-data volume and no extra hardware overhead for at-speed transition fault test. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed method.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129682608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：