A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Rei-Fu Huang, Jin-Fu Li, J. Yeh, Cheng-Wen Wu
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引用次数: 53

Abstract

We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.
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一种评估可修嵌入式存储器冗余分析算法的模拟器
我们提出了一个评估冗余分析(RA)算法的模拟器。仿真器可以计算给定RA算法的修复率(修复的存储器数量与有缺陷的存储器数量之比)以及相应的存储器配置和冗余结构。使用该工具,用户还可以轻松评估和规划冗余(备用)元件,并随后开发内置冗余分析(BIRA)算法和电路,这些算法和电路对于嵌入式存储器的内置自我修复(BISR)至关重要。该仿真器的另一个重要特点是能够按真实的顺序模拟检测到的故障序列,提高了分析结果的准确性。
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