Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029778
Thierry Devoivre, M. Lunenborg, C. Julien, J. Carrere, P. Ferreira, W. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond
This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16/spl Aring/ EOT-70nm transistors (standard process) or 21/spl Aring/-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1 Mbit SRAM instances, based on a highly manufacturable 6T 1.36/spl mu/m/sup 2/ memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.
{"title":"Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC)","authors":"Thierry Devoivre, M. Lunenborg, C. Julien, J. Carrere, P. Ferreira, W. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond","doi":"10.1109/MTDT.2002.1029778","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029778","url":null,"abstract":"This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16/spl Aring/ EOT-70nm transistors (standard process) or 21/spl Aring/-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1 Mbit SRAM instances, based on a highly manufacturable 6T 1.36/spl mu/m/sup 2/ memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120966794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029781
R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, J. Mirabel
This paper presents a study of EEPROM cell programming in order to decrease the bias polarization of the memory cell. Simulations show that it is possible to erase and write a cell with a divide up polarization, with positive and negative pulses. Measurements on a memory cell confirm these statements. Moreover simulations of the electrical field through the tunnel oxide didn't show any change of the maximum value, that means there is no impact on cell reliability. Endurance tests were performed on several memory cells with divide up polarizations. They show the same results as classical programming.
{"title":"Decreasing EEPROM programming bias with negative voltage, reliability impact","authors":"R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, J. Mirabel","doi":"10.1109/MTDT.2002.1029781","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029781","url":null,"abstract":"This paper presents a study of EEPROM cell programming in order to decrease the bias polarization of the memory cell. Simulations show that it is possible to erase and write a cell with a divide up polarization, with positive and negative pulses. Measurements on a memory cell confirm these statements. Moreover simulations of the electrical field through the tunnel oxide didn't show any change of the maximum value, that means there is no impact on cell reliability. Endurance tests were performed on several memory cells with divide up polarizations. They show the same results as classical programming.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131561517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029769
S. Hamdioui, A. V. Goor, M. Rodgers
This paper presents all simple (i.e., not linked) static fault models that have been shown to exist for random access memories (RAMs), and shows that none of the current industrial march tests has the capability to detect all these faults. It therefore introduces a new test (March SS), with a test length of 22n, that detects all realistic simple static faults in RAMs.
{"title":"March SS: a test for all static simple RAM faults","authors":"S. Hamdioui, A. V. Goor, M. Rodgers","doi":"10.1109/MTDT.2002.1029769","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029769","url":null,"abstract":"This paper presents all simple (i.e., not linked) static fault models that have been shown to exist for random access memories (RAMs), and shows that none of the current industrial march tests has the capability to detect all these faults. It therefore introduces a new test (March SS), with a test length of 22n, that detects all realistic simple static faults in RAMs.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131577768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029774
J. Portal, L. Forli, H. Aziza, D. Née
The objective of this paper is to present an Automated Design methodology for EEPROM cell (ADE). This method focuses on EEPROM cell geometry automatic generation for a targeted program window including constraints like robustness to process variation, program high voltage and electric field minimization. The method is based on a mathematical model generated with a "Design Of Simulation" (DOS) technique. The DOS technique takes as input, simulations results of a floating gale transistor for different given geometries and program high voltages. It produces, as output, polynomial equations of the threshold voltages and maximal electric field injunction of the geometric parameters and of the program high voltage. Using those equations, the design process is realized in two steps. In a first step, a set of cells (geometry and high voltage) meeting a targeted threshold voltages window is generated. From this set of cells, the optimal cell is selected under robustness, high voltage and electric field minimization criteria.
{"title":"An automated design methodology for EEPROM cell (ADE)","authors":"J. Portal, L. Forli, H. Aziza, D. Née","doi":"10.1109/MTDT.2002.1029774","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029774","url":null,"abstract":"The objective of this paper is to present an Automated Design methodology for EEPROM cell (ADE). This method focuses on EEPROM cell geometry automatic generation for a targeted program window including constraints like robustness to process variation, program high voltage and electric field minimization. The method is based on a mathematical model generated with a \"Design Of Simulation\" (DOS) technique. The DOS technique takes as input, simulations results of a floating gale transistor for different given geometries and program high voltages. It produces, as output, polynomial equations of the threshold voltages and maximal electric field injunction of the geometric parameters and of the program high voltage. Using those equations, the design process is realized in two steps. In a first step, a set of cells (geometry and high voltage) meeting a targeted threshold voltages window is generated. From this set of cells, the optimal cell is selected under robustness, high voltage and electric field minimization criteria.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127163346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029775
C. Dray, P. Gendrier
Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.
{"title":"A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology","authors":"C. Dray, P. Gendrier","doi":"10.1109/MTDT.2002.1029775","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029775","url":null,"abstract":"Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029773
M. Redeker, B. Cockburn, D. Elliott
The 2001 ITRS roadmap predicts continued aggressive progress towards deep submicron linewidths for at least the next 15 years. In this article we describe the results of a simulation study into the effects of crosstalk among DRAM wordlines and bitlines for present and future technology nodes predicted by the roadmap. An analog simulator was used to solve the associated transmission line equations derived from Maxwell's equations in the time domain. Hence, we not only considered interconnect resistances and capacitances, but also inductances and realistic wave propagation effects. The circuit parameters of the simulation models were extracted from standard DRAM geometries implied by the roadmap data. Various bitline-bitline and wordline-wordline coupling scenarios were then studied in simulation. Our results suggest that down until the 22-nm node, single bitline twisting will continue to be effective against bitline-bitline coupling, but that wordline-wordline coupling effects will become more problematic.
{"title":"An investigation into crosstalk noise in DRAM structures","authors":"M. Redeker, B. Cockburn, D. Elliott","doi":"10.1109/MTDT.2002.1029773","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029773","url":null,"abstract":"The 2001 ITRS roadmap predicts continued aggressive progress towards deep submicron linewidths for at least the next 15 years. In this article we describe the results of a simulation study into the effects of crosstalk among DRAM wordlines and bitlines for present and future technology nodes predicted by the roadmap. An analog simulator was used to solve the associated transmission line equations derived from Maxwell's equations in the time domain. Hence, we not only considered interconnect resistances and capacitances, but also inductances and realistic wave propagation effects. The circuit parameters of the simulation models were extracted from standard DRAM geometries implied by the roadmap data. Various bitline-bitline and wordline-wordline coupling scenarios were then studied in simulation. Our results suggest that down until the 22-nm node, single bitline twisting will continue to be effective against bitline-bitline coupling, but that wordline-wordline coupling effects will become more problematic.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127550014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029772
M. Redeker, B. Cockburn, D. Elliott, Y. Xiang, S. A. Ung
Multilevel dynamic random-access memory (MLDRAM) attempts to increase the storage density of semiconductor memory without further reducing the lithographic dimensions. It does so by using more than two possible signal voltages on each cell capacitor thus permitting more than one bit to be stored in each cell. Birk's MLDRAM scheme has several promising properties, including robust locally-generated data signal and reference signal generation, and fast flash-conversion sensing. This paper describes a fault model for Birk's MLDRAM that was developed by considering the behaviors produced by likely defects at the schematic level. The resulting behaviors include faults that are detectable as observable logical errors, faults that can be detected by current measurements, and faults that, in the worst case, can only be detected by testing for degraded noise margins. All Boolean faults in the fault model can be detected by an efficient test whose length grows linearly in the number of cells. The narrower noise margins in MLDRAM will make it more vulnerable to pattern sensitivities. We also developed a linear test that evaluates worst-case sensing conditions.
{"title":"Fault modeling and pattern-sensitivity testing for a multilevel DRAM","authors":"M. Redeker, B. Cockburn, D. Elliott, Y. Xiang, S. A. Ung","doi":"10.1109/MTDT.2002.1029772","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029772","url":null,"abstract":"Multilevel dynamic random-access memory (MLDRAM) attempts to increase the storage density of semiconductor memory without further reducing the lithographic dimensions. It does so by using more than two possible signal voltages on each cell capacitor thus permitting more than one bit to be stored in each cell. Birk's MLDRAM scheme has several promising properties, including robust locally-generated data signal and reference signal generation, and fast flash-conversion sensing. This paper describes a fault model for Birk's MLDRAM that was developed by considering the behaviors produced by likely defects at the schematic level. The resulting behaviors include faults that are detectable as observable logical errors, faults that can be detected by current measurements, and faults that, in the worst case, can only be detected by testing for degraded noise margins. All Boolean faults in the fault model can be detected by an efficient test whose length grows linearly in the number of cells. The narrower noise margins in MLDRAM will make it more vulnerable to pattern sensitivities. We also developed a linear test that evaluates worst-case sensing conditions.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029760
B. Coloma, P. Delaunay, O. Husson
A high speed 15 ns 4 Mbit asynchronous SRAM, 500 /spl mu/A stand-by current, 300 krad total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allowing mitigation with classical EDAC corrector. The product operates within 3 to 3.6 V, and ambient temperature from -55 to +125/spl deg/C. A high density die size of 68.3 mm/sup 2/ allows the use of a specific 36-pins dual in line flat pack package with a 500 mil width, making this product very competitive against SEU hardened chips. Successful silicon results are presented as well as radiation tests up to 300 krad.
{"title":"High speed 15 ns 4 Mbit SRAM for space application","authors":"B. Coloma, P. Delaunay, O. Husson","doi":"10.1109/MTDT.2002.1029760","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029760","url":null,"abstract":"A high speed 15 ns 4 Mbit asynchronous SRAM, 500 /spl mu/A stand-by current, 300 krad total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allowing mitigation with classical EDAC corrector. The product operates within 3 to 3.6 V, and ambient temperature from -55 to +125/spl deg/C. A high density die size of 68.3 mm/sup 2/ allows the use of a specific 36-pins dual in line flat pack package with a 500 mil width, making this product very competitive against SEU hardened chips. Successful silicon results are presented as well as radiation tests up to 300 krad.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128945945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029761
D. Bied-Charreton, D. Guillon, B. Jacques
This paper deals with some aspects of the use of self-checking integrated circuits in an application that manages the major risks involved in a transport system. It aims to provide an objective account of the advantages and disadvantages of this type of technology. Attention has been focused on the demands made by such integrated circuits on their environment, in particular the CPUs which control them. Nevertheless, much work still needs to be done to bring the design and testing of integrated circuits more in line with the needs of rail safety applications.
{"title":"The YATE fail-safe interface: the user's point of view","authors":"D. Bied-Charreton, D. Guillon, B. Jacques","doi":"10.1109/MTDT.2002.1029761","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029761","url":null,"abstract":"This paper deals with some aspects of the use of self-checking integrated circuits in an application that manages the major risks involved in a transport system. It aims to provide an objective account of the advantages and disadvantages of this type of technology. Attention has been focused on the demands made by such integrated circuits on their environment, in particular the CPUs which control them. Nevertheless, much work still needs to be done to bring the design and testing of integrated circuits more in line with the needs of rail safety applications.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-10DOI: 10.1109/MTDT.2002.1029768
M. Hashimoto
A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64 Mb DRAM array.
{"title":"Adder merged DRAM architecture","authors":"M. Hashimoto","doi":"10.1109/MTDT.2002.1029768","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029768","url":null,"abstract":"A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64 Mb DRAM array.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128465854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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