{"title":"A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology","authors":"C. Dray, P. Gendrier","doi":"10.1109/MTDT.2002.1029775","DOIUrl":null,"url":null,"abstract":"Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.
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