E. Maayan, R. Dvir, J. Shor, Y. Polansky, Y. Sofer, I. Bloom, D. Avni, B. Eitan, Z. Cohen, M. Meyassed, Y. Alpern, H. Palm, E.S. v Kamienski, P. Haibach, D. Caspary, Sebastian Riedel, R. Knofler
{"title":"A 512 Mb NROM flash data storage memory with 8 MB/s data rate","authors":"E. Maayan, R. Dvir, J. Shor, Y. Polansky, Y. Sofer, I. Bloom, D. Avni, B. Eitan, Z. Cohen, M. Meyassed, Y. Alpern, H. Palm, E.S. v Kamienski, P. Haibach, D. Caspary, Sebastian Riedel, R. Knofler","doi":"10.1109/ISSCC.2002.992958","DOIUrl":null,"url":null,"abstract":"The NROM technology is applied to EEPROM, flash, and data storage product lines. All the products are based on the two-bit-per-cell core technology, using common design concepts, algorithms, circuits, and the same process architecture. Differing product requirements emphasize the versatility of the concept.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
The NROM technology is applied to EEPROM, flash, and data storage product lines. All the products are based on the two-bit-per-cell core technology, using common design concepts, algorithms, circuits, and the same process architecture. Differing product requirements emphasize the versatility of the concept.
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