Background calibration techniques for multistage pipelined ADCs with dynamic element matching and pseudorandom noise

Abstract

Based on dynamic element matching (DEM) and pseudorandom noise (PN), a digital background calibration scheme, applicable to mu ltistage pipelined analog-to-digital converters (PADCs), to correct the linearity errors resulting from capacitance mismatches is presented. This calibration technique scheme takes advantage of the PN sequence to extract linearity errors and DEM to make sure the errors of all the capacitances can be extracted. In the proposed method, capacitance mismatches are corrected, while the SNR is not degraded for the pseudorandom noise sequence injected into the system. Experimental results show that ENOB is 10.96 bits and SFDR achieves 85.1230 dB.