Challenges and Approaches of 2.5D high density Flip chip interconnect on through mold interposer

Abstract

The continuous requirements of package miniaturization in the demand of mobile application market have shown the increase in demand of many FOWLP packaging [1]. The applications of FOWLP has many advantages including shorter interconnection, lower heat resistance, better electrical efficiency and smaller package form factor [2].The work presented in this paper describes the reconfigured wafer approach in fan-out wafer level technology that allows multiple dies with high solder interconnect to package using the molded interposer for FOWLP technology. In this work, we presented some of the work done prior to the flip chip bonding process and the different approaches to resolve some of the process issues encountered in the assembly process for 3 test dies with high I/Os onto a fan-out mold interposer. The 1st test die is the 15x15mm ASIC die with 21472 I/Os and the remaining 2 dies are the 7x7mm HBM dies with 4942 I/Os. Both the ASIC and HBM dies have a minimum bump pitch at 55 μ m. The 12 inch through molded interposer wafer is singulated into individual interposer prior to the flip chip attachment process.The package warpage remains the main concern in the through mold interposer assembly. To minimize interposer warpage, a metal stiffener was attached to the molded interposer. Results shows the attachment of the metal stiffener helps to reduce the package warpage. In addition, a thinner die thickness of 150 μ m helps to reduce the overall molded interposer package‘s warpage after assembly compared to a die thickness of 500 μ m. Cross-section analysis was done to inspect the solderjoint shape at 150 μ m and 500 μ m die thickness. Further optimized thermocompression bonding process and capillary underfill process helps to ensure good solderjoint interconnection and no underfill voids for a robust Fine pitch interconnect Fan-out WLP assembly.